SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to read the interrupt signal for each slot.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 00FCh |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| INTR_SIG | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:8 | RESERVED | NONE | 0h | Reserved |
| 7:0 | INTR_SIG | R | 0h | These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. Reset Source: vbus_amod_g_rst_n |