SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to enable the UHS-II Error Interrupt Status register fields
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 00C8h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| VENDOR_SPECFIC | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| RESERVED | DEADLOCK_TIMEOUT | CMD_RESP_TIMEOUT | |||||
| NONE | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| ADMA2_ADMA3 | RESERVED | EBSY | |||||
| R/W | NONE | R/W | |||||
| 0h | 0h | 0h | |||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| UNRECOVERABLE | RESERVED | TID | FRAMING | CRC | RETRY_EXPIRED | RESP_PKT | HEADER |
| R/W | NONE | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:27 | VENDOR_SPECFIC | R/W | 0h | Setting this bit to 1 enables setting of Vendor Specific Error bit in the UHS-II Error Interrupt Status register. 0h - Status is Disabled 1h - Status is Enabled Reset Source: vbus_amod_g_rst_n |
| 26:18 | RESERVED | NONE | 0h | Reserved |
| 17 | DEADLOCK_TIMEOUT | R/W | 0h |
Setting this bit to 1 enables setting of Timeout for Dead lock bit in the UHS-II Error Interrupt Status register.
1 Status is Enabled 0 Status is Disabled |
| 16 | CMD_RESP_TIMEOUT | R/W | 0h |
Setting this bit to 1 enables setting of Timeout for CMD_RES bit in the UHS-II Error Interrupt Status register.
1 Status is Enabled 0 Status is Disabled |
| 15 | ADMA2_ADMA3 | R/W | 0h |
Setting this bit to 1 enables setting of ADMA2/3 Error bit in the UHS-II Error Interrupt Status register.
1 Status is Enabled 0 Status is Disabled |
| 14:9 | RESERVED | NONE | 0h | Reserved |
| 8 | EBSY | R/W | 0h |
Setting this bit to 1 enables setting of EBSY Error bit in the UHS-II Error Interrupt Status register.
1 Status is Enabled 0 Status is Disabled |
| 7 | UNRECOVERABLE | R/W | 0h |
Setting this bit to 1 enables setting of Unrecoverable Error bit in the UHS-II Error Interrupt Status register.
1 Status is Enabled 0 Status is Disabled |
| 6 | RESERVED | NONE | 0h | Reserved |
| 5 | TID | R/W | 0h |
Setting this bit to 1 enables setting of TID Error bit in the UHS-II Error Interrupt Status register.
1 Status is Enabled 0 Status is Disabled |
| 4 | FRAMING | R/W | 0h |
Setting this bit to 1 enables setting of Framing Error bit in the UHS-II Error Interrupt Status register.
1 Status is Enabled 0 Status is Disabled |
| 3 | CRC | R/W | 0h |
Setting this bit to 1 enables setting of CRC Error bit in the UHS-II Error Interrupt Status register.
1 Status is Enabled 0 Status is Disabled |
| 2 | RETRY_EXPIRED | R/W | 0h |
Setting this bit to 1 enables setting of Retry Expired bit in the UHS-II Error Interrupt Status register.
1 Status is Enabled 0 Status is Disabled |
| 1 | RESP_PKT | R/W | 0h |
Setting this bit to 1 enables setting of RES Packet Error bit in the UHS-II Error Interrupt Status register.
1 Status is Enabled 0 Status is Disabled |
| 0 | HEADER | R/W | 0h |
Setting this bit to 1 enables setting of Header Error bit in the UHS-II Error Interrupt Status Register.
1 Status is Enabled 0 Status is Disabled |