SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register gives the status of all UHS-II interrupts
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 00C4h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| VENDOR_SPECFIC_ERR | RESERVED | ||||||
| R/W1TC | NONE | ||||||
| 0h | 0h | ||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| RESERVED | DEADLOCK_TIMEOUT | CMD_RESP_TIMEOUT | |||||
| NONE | R/W1TC | R/W1TC | |||||
| 0h | 0h | 0h | |||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| ADMA2_ADMA3 | RESERVED | EBSY | |||||
| R/W1TC | NONE | R/W1TC | |||||
| 0h | 0h | 0h | |||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| UNRECOVERABLE | RESERVED | TID | FRAMING | CRC | RETRY_EXPIRED | RESP_PKT | HEADER |
| R/W1TC | NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:27 | VENDOR_SPECFIC_ERR | R/W1TC | 0h | Vendor may use this field for vendor specific error status. '0' Interrupt is not generated '1' Vendor Specific Error Reset Source: vbus_amod_g_rst_n |
| 26:18 | RESERVED | NONE | 0h | Reserved |
| 17 | DEADLOCK_TIMEOUT | R/W1TC | 0h |
Setting of this bit means that deadlock timeout occurs. Host expects to receive a packet but not received in a specified timeout [1 second]. Timeout value is determined by the setting of Timeout Counter Value for Deadlock in UHS-II Timer Control register.
1 Deadlock Error 0 No Error |
| 16 | CMD_RESP_TIMEOUT | R/W1TC | 0h |
Setting of this bit means that RES Packet timeout occurs. Host expects to receive RES packet but not received in a specified timeout [5ms]. Timeout value is determined by the setting of Timeout Counter Value for CMD_RES in UHS-II Timer Control register.
1 Resp packet timeout Error 0 No Error |
| 15 | ADMA2_ADMA3 | R/W1TC | 0h |
Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode. ADMA2/3 Error Status is indicated to the ADMA Error Status [054h], which is defined in the Host spec 3.00.
1 ADMA2/3 Error 0 No Error |
| 14:9 | RESERVED | NONE | 0h | Reserved |
| 8 | EBSY | R/W1TC | 0h |
On receiving EBSY packet, if the packet indicates an error, this bit is set to 1. Setting of this bit also sets Error Interrupt and Transfer Completer together in the Normal Interrupt Status register. This error check is effective for a command with setting EBSY Wait in the UHS-II Transfer Mode register.
1 EBSY Error 0 No Error |
| 7 | UNRECOVERABLE | R/W1TC | 0h |
Setting of this bit means that Unrecoverable Error is set in a packet from a device.
1 Device Unrecoverable Error 0 No Error |
| 6 | RESERVED | NONE | 0h | Reserved |
| 5 | TID | R/W1TC | 0h |
Setting of this bit means that TID Error occurs.
1 TID Error 0 No Error |
| 4 | FRAMING | R/W1TC | 0h |
Setting of this bit means that Framing Error occurs during a packet receiving.
1 Framing Error 0 No Error |
| 3 | CRC | R/W1TC | 0h |
Setting of this bit means that CRC Error occurs during a packet receiving.
1 CRC Error 0 No Error |
| 2 | RETRY_EXPIRED | R/W1TC | 0h |
Setting of this bit means that Retry Counter Expired Error occurs during data transfer.If this bit is set,either Framing Error or CRC Error in this register shall be set.
1 Retry Expired Error 0 No Error |
| 1 | RESP_PKT | R/W1TC | 0h |
Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to1 in the UHS- II Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response,this bit is set to 1.
1 Resp packet Error 0 No Error |
| 0 | HEADER | R/W1TC | 0h |
Setting of this bit means that Header Error occurs in a received packet.
1 Header Error 0 No Error |