SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
UHS-II Timeout Control Register
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 00C2h |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| DEADLOCK_TIMEOUT_CTR | CMDRESP_TIMEOUT_CTR | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:8 | RESERVED | NONE | 0h | Reserved |
| 7:4 | DEADLOCK_TIMEOUT_CTR | R/W | 0h | This value determines the deadlock period while host expecting to receive a packet [1 second]. Tim-eout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this register, prevent inadvertent timeout events by clearing the Timeout for Deadlock [in the UHS-II Error Interrupt Status Enable register] 1111b Reserved 1110b TMCLK x 2^27 .............. .................. 0001b TMCLK x 2^14 0000b TMCLK x 2^13 Reset Source: vbus_amod_g_rst_n |
| 3:0 | CMDRESP_TIMEOUT_CTR | R/W | 0h | This value determines the interval between com-mand packet and response packet [5ms]. Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When set-ting this register, prevent inadvertent timeout events by clearing the Timeout for CMD_RES [in the UHS-II Error Interrupt Status Enable register] 1111b Reserved 1110b TMCLK x 2^27 .............. .................. 0001b TMCLK x 2^14 0000b TMCLK x 2^13 Reset Source: vbus_amod_g_rst_n |