SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register shows receipt of INT MSG from which device
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 00BCh |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| DEV_INT_STS | |||||||
| R/W1TC | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| DEV_INT_STS | |||||||
| R/W1TC | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:0 | DEV_INT_STS | R/W1TC | 0h | This register shows receipt of INT MSG from which device and is effective when INT MSG Enable is set to 1 in the UHS- II Device Select register. On receiving INT MSG from a device, Host Controller saves the INT MSG to UHS-II Device Interrupt Code register. A bit of this register, which is corre- spondent to Device ID, is set to 1 and generate Card Interrupt in Normal Interrupt Status register. Writing a bit to 1 clears the status bit [interrupt is treated] and writing a bit to 0 keeps the status value [interrupt is untreated]. If INT MSG Enable is set to 0, this register is cleared to 0 and Host Controller ignores receipt of INT MSG. Effective bit range of this register is determined by Number of Devices Supported in the UHS-II General Capabilities regis-ter. If N devices are supported, bits 1 to N are effective. Then Device ID is supposed to be assigned from 1 sequentially at the UHS-II Initialization. A bit of unsupported Device ID in this register shall be indicated to 0. D00 - Not used [Reserved] D01 - Setting 1 means INT MSG is received from Device ID 1 D02 - Setting 1 means INT MSG is received from Device ID 2 .... ..... D15 - Setting 1 means INT MSG is received from Device ID 15 Reset Source: vbus_amod_g_rst_n |