SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to program the Command for host controller
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 009Eh |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | PKT_LENGTH | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| CMD_TYPE | DATA_PRESENT | RESERVED | SUB_COMMAND | RESERVED | |||
| R/W | R/W | NONE | R/W | NONE | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:13 | RESERVED | NONE | 0h | Reserved |
| 12:8 | PKT_LENGTH | R/W | 0h | A command packet length, which is set in the UHS-II Command Packet register, is set to this register. 00011b - 00000b - 3-0 Bytes [Not used] 00100b - 4 Bytes .......... ...... 10100b - 20 Bytes 11111b 10101b Reset Source: vbus_amod_g_rst_n |
| 7:6 | CMD_TYPE | R/W | 0h |
This field is used to distinguish a spe-cific command like abort command. If this field is set to 00b, the UHS-II RES Packet is stored in UHS-II Response register [0B3h-0A0h]. To avoid overwrit-ing the UHS-II Response register, when this filed is set to 01b, the RES Packet [4 bytes length] of TRANS_ABORT CCMD is stored in the Response regis-ter [013h-010h] and when this filed is set to 10b, the RES Packet [8 bytes
length] of memory or SDIO abort com-mand [CMD12 or SDIO Abort com-mand] is stored in the Response register [01Fh-018h]. When this filed is set to 11b, Host Controller controls lane to go into dormant state.
'00' Normal Command
'01' TRANS_ABORT CCMD
'10' CMD12 or SDIO Abort Command
'11' Go Dormant Command
3 2 1 0 |
| 5 | DATA_PRESENT | R/W | 0h | This bit specifies whether the command is accompanied by data packet.
1 Data present 0 Data not Present |
| 4:3 | RESERVED | NONE | 0h | Reserved |
| 2 | SUB_COMMAND | R/W | 0h | This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17].When issuing a main command, this bit
is set to 0 and when issuing a sub com-mand, this bit is set to 1. Setting of this bit is checked by Sub Command Status in the Present State register.
1 Sub Command 0 Main Command |
| 1:0 | RESERVED | NONE | 0h | Reserved |