SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to control the operations of data transfers
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 009Ch |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| DUPLEX_SELECT | EBSY_WAIT | RESERVED | RESP_INTR_DIS | ||||
| R/W | R/W | NONE | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| RESP_ERR_CHK_ENA | RESP_TYPE | BYTE_MODE | DATA_XFER_DIR | RESERVED | BLK_CNT_ENA | DMA_ENA | |
| R/W | R/W | R/W | R/W | NONE | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | DUPLEX_SELECT | R/W | 0h |
Use of 2 lane half duplex mode is determined by Host Driver.
1 0 |
| 14 | EBSY_WAIT | R/W | 0h | This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution. Busy is expected for CCMD with R1b/R5b type and DCMD with data transfer.If this bit is set to 1, Host Controller waits receiving of EBSY packet and on receiving EBSY packet, Transfer Com-plete in the Normal Interrupt Status reg-ister is set to 1 to indicate end ofbusy. If an error is indicated in EBSY packet [ex. Memory Error], EBSY Error in the UHS-II Error Interrupt Status register is set to 1. Setting of EBSY Error also sets Error Interrupt to 1 in the Normal Inter-rupt Status register. Error Interrupt and Transfer Complete shall be set together. '1' Wait EBSY, '0' Issue a command without busy. Reset Source: vbus_amod_g_rst_n |
| 13:9 | RESERVED | NONE | 0h | Reserved |
| 8 | RESP_INTR_DIS | R/W | 0h |
Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked.
If Host Driver checks response error, sets this bit to 0 and waits Command Complete Interrupt and then check the response register. If Host Controller checks response error, sets this bit to 1 and sets Response Error Check Enable to 1. Command Complete Interrupt is disabled by this bit regardless of Com-mand Complete Signal Enable.
1 Disable Response Interrupt 0 Enable Response Interrupt |
| 7 | RESP_ERR_CHK_ENA | R/W | 0h |
Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver.Only R1 or R5 can be checked.
If Host Driver checks response error, this bit is set to 0 and Response Inter-rupt Disable is set to 0. If Host Control-ler checks response error, sets this bit to 1 and sets Response Interrupt Dis-able to 1. Response Type R1 / R5 selects either R1 or R5 response type. If an error is detected, RES Packet Error Interrupt is generated in the UHS-II Error Interrupt Status register.
1 Enable Response Error Check 0 Disable Response Error Check |
| 6 | RESP_TYPE | R/W | 0h |
When response error check is enabled, this bit selects either R1 or R5 response
types. Two types of response checks are supported: R1 for memory and R5 for SDIO.
Error Statuses Checked in R1
Bit31 OUT_OF_RANGE
Bit30 ADDRESS_ERROR
Bit29 BLOCK_LEN_ERROR
Bit26 WP_VIOLATION
Bit25 CARD_IS_LOCKED
Bit23 COM_CRC_ERROR
Bit21 CARD_ECC_FAILED
Bit20 CC_ERROR
Bit19 ERROR
Response Flags Checked in R5
.Bit07 COM_CRC_ERROR
.Bit03 ERROR
.Bit01 FUNCTION_NUMBER
.Bit00 OUT_OF_RANGE
1 SDIO 0 Memory |
| 5 | BYTE_MODE | R/W | 0h |
This bit specifies whether data transfer is in byte mode or block mode when Data Present is set to 1. This bit is effective to a command with data trans-fer.
1 0 |
| 4 | DATA_XFER_DIR | R/W | 0h |
This bit specifies direction of data trans-fer when Data Present is set to 1. This bit is effective to a command with data transfer.
0 - Read [Card to Host]
1 - Write [Host to Card]
1 Write from Host to Card 0 Read from Card to Host |
| 3:2 | RESERVED | NONE | 0h | Reserved |
| 1 | BLK_CNT_ENA | R/W | 0h |
This bit specifies whether data transfer usesUHS-II Block Count register. If this bit is set to 1, data transfer is terminated by Block Count. Setting to UHS-II Block Count register shall be equivalent to TLEN in UHS-II Command Packet reg-ister.
1 Enable Block count 0 Disable Block count |
| 0 | DMA_ENA | R/W | 0h | This bit selects whether DMA is used or not and is effective to a command with data transfer. One of DMA types is selected by DMA Select in the Host Control 1 register.
1 DMA mode is Enabled 0 DMA mode is Disabled |