SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to configure the number of bytes in a data block
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0080h |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | SDMA_BUF_BOUNDARY | XFER_BLK_SIZE | |||||
| NONE | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| XFER_BLK_SIZE | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | NONE | 0h | Reserved |
| 14:12 | SDMA_BUF_BOUNDARY | R/W | 0h |
When system memory is managed by paging, SDMA data transfer is performed in unit of paging. A page size of sys-tem memory management is set to this field.
Host Controller generates the DMA Interrupt at the page boundary and requests the Host Driver to update the ADMA System Address register. SDMA waits until the ADMA System Address register is written.
At the end of transfer, the Host Controller may issue or may not issue DMA Interrupt. In particular, DMA Interrupt shall not be issued after Transfer Complete Interrupt is issued.
These bits shall be supported when the SDMA Support in the Capabilities register is set to 1 and this function is active when the DMA Enable in the UHS-II Transfer Mode register is set to 1. ADMA does not use this field.
7 6 5 4 3 2 1 0 |
| 11:0 | XFER_BLK_SIZE | R/W | 0h | This register specifies the block size of data packet. SD Memory Card uses a fixed block size of 512 bytes. Vari-able block size may be used for SDIO. The maximum value is 2048 Bytes because CRC16 covers up to 2048 bytes. This register is effective when Data Present is set to 1 in UHS-II Command register.
2048 512 2 1 0 |