SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The start address of Integrated DMA Descriptor is set to this register.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0078h |
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | |
| INTG_DESC_ADDR | |||||||
| R/W | |||||||
| 0h | |||||||
| 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 |
| INTG_DESC_ADDR | |||||||
| R/W | |||||||
| 0h | |||||||
| 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 |
| INTG_DESC_ADDR | |||||||
| R/W | |||||||
| 0h | |||||||
| 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 |
| INTG_DESC_ADDR | |||||||
| R/W | |||||||
| 0h | |||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| INTG_DESC_ADDR | |||||||
| R/W | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| INTG_DESC_ADDR | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 63:0 | INTG_DESC_ADDR | R/W | 0h | The start address of Integrated DMA Descriptor is set to this register. Writing to a specific address starts ADMA3 depends on 32-bit/64-bit address-ing. The ADMA3 fetches one Descriptor Address and increments this field to indicate the next Descriptor address. The 32-bit addressing Host Driver uses lower 32- bit of this register and shall program Descriptor Table on 32-bit boundary.ADMA3 ignores lower 2-bit of this register and assumes it to be 00b. Writing to 07Bh starts ADMA3 data transfer. The 64-bit addressing Host Driver uses all 64-bit of this register and shall program Descriptor Table on 64-bit boundary. ADMA3 ignores lower 3-bit of this register and assumes it to be 000b. Writing to 07Fh starts ADMA3 data transfer. Register Value- 00000000_xxxxxxxxh Addressing Mode - 32-bit System Address Register Value - xxxxxxxx_xxxxxxxxh Addressing Mode - 64-bit System Address Reset Source: vbus_amod_g_rst_n |