SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to read the SDCLK Frequency Select Value,Clock Generator Select Value,Driver Strength Select Value
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0064h |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| DRIVER_STRENGTH_SEL | RESERVED | CLOCK_GENSEL | SDCLK_FRQSEL | ||||
| R | NONE | R | R | ||||
| 0h | 0h | 0h | 2h | ||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| SDCLK_FRQSEL | |||||||
| R | |||||||
| 2h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:14 | DRIVER_STRENGTH_SEL | R | 0h | Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
3 2 1 0 |
| 13:11 | RESERVED | NONE | 0h | Reserved |
| 10 | CLOCK_GENSEL | R | 0h | This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator Reset Source: vbus_amod_g_rst_n |
| 9:0 | SDCLK_FRQSEL | R | 2h | 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. Reset Source: vbus_amod_g_rst_n |