SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the physical address used for ADMA data transfer
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0058h |
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | |
| ADMA_ADDR | |||||||
| R/W | |||||||
| 0h | |||||||
| 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 |
| ADMA_ADDR | |||||||
| R/W | |||||||
| 0h | |||||||
| 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 |
| ADMA_ADDR | |||||||
| R/W | |||||||
| 0h | |||||||
| 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 |
| ADMA_ADDR | |||||||
| R/W | |||||||
| 0h | |||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| ADMA_ADDR | |||||||
| R/W | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| ADMA_ADDR | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 63:0 | ADMA_ADDR | R/W | 0h | The 32-bit addressing Host Driver uses lower 32-bit of this register [upper 32-bit should be set to 0] and shall program Descriptor Table on 32-bit boundary andset 32-bit boundary address to this register. DMA2/3 ignores lower 2-bit of this register and assumes it to be 00b. DMA in 64-bit addressing. The 64-bit addressing Host Driver uses all bits of this register and shall program Descriptor Table on 64-bit boundary and set 64-bit boundary address to this register. DMA2/3 ignores lower 3-bit of this register andassumes it to be 000b. SDMA If Host Version 4.00 Enable is set to 1, SDMA use this register to indicate System Address of data location instead of using SDMA System Address register [Offset 003-000h]. SDMA can be used in 32-bit and 64-bit addressing in Version 4.00. ADMA2 This register holds byte address of executing command of the Descriptor table. At the start of ADMA2, the Host Driver shall set start address of the Descriptor table. The ADMA increments this register address, which points to next line, when every fetching a Descriptor line. When the ADMA Error Interrupt is generated, this register shall hold the Descriptor address depending on the ADMA state. ADMA3 This register is set by ADMA3. Host Driver is not necessary to set this register. The ADMA3 increments address of this register,which points to next line, when every time fetching a Descriptor line. When Error Interrupt is generated, this register shall hold the Descriptor address depending on the ADMA state. Register Value - 00000000_xxxxxxxxh Addressing Mode - 32-bit System Address Register Value - xxxxxxxx_xxxxxxxxh Addressing Mode - 64-bit System Address Reset Source: vbus_amod_g_rst_n |