SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
When the ADMA Error interrupt occur, this register holds the ADMA State in ADMA Error States field and ADMA System Address holds address around the error descriptor
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0054h |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| RESERVED | ADMA_LENGTH_ERR | ADMA_ERR_STATE | |||||
| NONE | R | R | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:3 | RESERVED | NONE | 0h | Reserved |
| 2 | ADMA_LENGTH_ERR | R | 0h |
This error occurs in the following 2 cases.
While Block Count Enable being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. Total data length can not be divided by the block length.
1 Error set 0 No Error |
| 1:0 | ADMA_ERR_STATE | R | 0h |
This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates "10" because ADMA never stops in this state.
D01 D00 : ADMA Error State when error occurred Contents of SYS_SDR register.
3 ST_TFR(Transfer Data) Points to the next of
the error descriptor
2 Never set this state(Not Used)
1 ST_FDS(Fetch Descriptor)Points to the error
descriptor
0 ST_STOP(Stop DMA) Points to next of the
error descriptor |