SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is not physically implemented, rather it is an address where Auto CMD Error Status register can be written. Writing 1 : set each bit of the Auto CMD12 Error Status Register Writing 0 : no effect.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0050h |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| CMD_NOT_ISS | RESERVED | RESP | INDEX | ENDBIT | CRC | TIMEOUT | ACMD_NOT_EXEC |
| W | NONE | W | W | W | W | W | W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:8 | RESERVED | NONE | 0h | Reserved |
| 7 | CMD_NOT_ISS | W | 0h |
Force Event for Command Not Issued by AUTO CMD12 Error.
1 Interrupt is generated 0 No Interrupt |
| 6 | RESERVED | NONE | 0h | Reserved |
| 5 | RESP | W | 0h |
Force Event for AUTO CMD Response Error..
1 Interrupt is generated 0 No Interrupt |
| 4 | INDEX | W | 0h |
Force Event for AUTO CMD Index Error..
1 Interrupt is generated 0 No Interrupt |
| 3 | ENDBIT | W | 0h |
Force Event for AUTO CMD End Bit Error.
1 Interrupt is generated 0 No Interrupt |
| 2 | CRC | W | 0h |
Force Event for AUTO CMD Timeout Error.
1 Interrupt is generated 0 No Interrupt |
| 1 | TIMEOUT | W | 0h |
Force Event for AUTO CMD Timeout Error.
1 Interrupt is generated 0 No Interrupt |
| 0 | ACMD_NOT_EXEC | W | 0h |
Force Event for AUTO CMD12 Not Executed.
1 Interrupt is generated 0 No Interrupt |