SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to program UHS Select Mode,UHS Select Mode,Driver Strength Select,Execute Tuning,Sampling Clock Select,Asynchronous Interrupt Enable and Preset value enable
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 003Eh |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| PRESET_VALUE_ENA | ASYNCH_INTR_ENA | BIT64_ADDRESSING | HOST_VER40_ENA | CMD23_ENA | ADMA2_LEN_MODE | DRIVER_STRENGTH2 | UHS2_INTF_ENABLE |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| SAMPLING_CLK_SELECT | EXECUTE_TUNING | DRIVER_STRENGTH1 | V1P8_SIGNAL_ENA | UHS_MODE_SELECT | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | PRESET_VALUE_ENA | R/W | 0h |
Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation, it is difficult to determine these parameters in the Standard Host Driver. When Preset Value Enable is set to automatic. This bit enables the functions defined in the Preset Value registers.
If this bit is set to 0, SDCLK Frequency Select, Clock Generator Select in the Clock Control register and Driver Strength Select in Host Control 2 register are set by Host Driver.
If this bit is set to 1, SDCLK Frequency Select, Clock Generator Select in the Clock Control register and Driver Strength Select in Host Control 2 register are set by Host Controller as specified in the Preset Value registers.
1 Automatic Selection by Preset Value are
Enabled
0 SDCLK and Driver Strength are controlled by
Host Driver |
| 14 | ASYNCH_INTR_ENA | R/W | 0h |
This bit can be set to 1 if a card support asynchronous interrupt and Asynchronous Interrupt Support is set to 1 in the Capabilities register. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode [and zero is set to Interrupt Pin Select in the Shared Bus Control register]. If this bit is set to 1, the Host Driver can stop the SDCLK during asynchronous interrupt period to save power. During this period, the Host Controller continues to deliver Card Interrupt to the host when it is asserted by the Card.
1 Asynchronous Interrupt enabled 0 Asynchronous Interrupt disabled |
| 13 | BIT64_ADDRESSING | R/W | 0h |
This field is effective when Host Version 4.00 Enable is set to 1.
Host Controller selects either of 32-bit or 64-bit addressing modes to access system memory. Whether 32-bit or 64-bit is determined by OS installed in a host system. Host Driver sets
this bit depends on addressing mode of installed OS. Refer to 64-bit System Address Support in the Capabilities register.
.
1 64 bit addressing 0 32 bit addressing |
| 12 | HOST_VER40_ENA | R/W | 0h |
This bit selects either Version 3.00 compatible mode or Ver4.mode. In Version 4.00, support of 64-bit System Addressing is modified. All DMAs support 64-bit System Addressing. UHS-II
supported Host Driver shall enable this bit. In Version 4.10, supported 32-bit Block Count for all operations. Functions of following fields are modified.
SDMA Address
SDMA uses ADMA System Address register [05Fh-058h] instead of SDMA System Address register [Offset 003-000h]
ADMA2 / ADMA3 Selection
ADMA3 is selected by DMA Select in the Host Control 1 regis-ter.
64bit ADMA Descriptor Size
128bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1.
Selection of 32-bit / 64-bit System Addressing
Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register instead of DMA Select in the Host Control 1 register.
32-bit Block Count
SDMA System Address register [003h-000h] is modified to 32-bit Block Count register.
1 Version 4 Mode 0 Version 3.00 Compatible Mode |
| 11 | CMD23_ENA | R/W | 0h |
In memory card initialization, Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]. If the card supports CMD23 [SCR[33]=1], this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 datatransfer. Refer to Auto CMD Enable in the Transfer Mode regis-ter.
1 CMD23 Enable 0 CMD23 Disable |
| 10 | ADMA2_LEN_MODE | R/W | 0h |
This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit.
1 26-bit Data Length Mode 0 16-bit Data Length Mode |
| 9 | DRIVER_STRENGTH2 | R/W | 0h | This is the programmed Drive STrength output and Bit[2] of the sdhccore_drivestrength value. Reset Source: vbus_amod_g_rst_n |
| 8 | UHS2_INTF_ENABLE | R/W | 0h |
This bit is used to enable UHS-II Interface. Before trying to start UHS-II initialization, this bit shall be set to 1. Before trying to start SD mode initialization, this bit shall be set to 0.
This bit is used to enable UHS-II IF Detection, Lane Synchroni-zation and In Dormant State in the Present State register, and to select clock source of either SD mode or UHS-II mode.
Host Controller shall not leave unused SD 4-bit Interface lines [CLK, CMD and DAT[3:2]] floating in UHS-II mode by using pull-up or driving to low. When DAT[2] is used as interrupt input in UHS-II mode, DAT[2] of Host Controller is set to input and then DAT[2] of SDIO card is set to output to avoid conflict.
'0' 4-bit SD Interface enabled
'1' UHS-II Interface enabled
1 UHS-II Interface enabled 0 4-bit SD Interface enabled |
| 7 | SAMPLING_CLK_SELECT | R/W | 0h |
This bit is set by tuning procedure when Execute Tuning is cleared. Writing 1 to this bit is meaningless and ignored. Setting 1 means that tuning is completed successfully and setting 0 means that tuning is failed. Host Controller uses this bit to select sampling clock to receive CMD and DAT. This bit is cleared by writing 0. Change of this bit is not allowed while the Host Controller is receiving response or a read data block.
1 Tuned clock is used to sample data 0 Fixed clock is used to sample data |
| 6 | EXECUTE_TUNING | R/W | 0h | This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to Sampling Clock Select. Tuning procedure is aborted by writing 0 for more detail about tuning procedure. '0' Not Tuned or Tuning Completed '1' Execute Tuning Reset Source: vbus_amod_g_rst_n |
| 5:4 | DRIVER_STRENGTH1 | R/W | 0h |
Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling, this field is not effective. This field can be set depends on Driver Type A, C and D support bits in the Capabilities register. This bit depends on setting of Preset Value Enable.
If Preset Value Enable = 0, this field is set by Host Driver.
If Preset Value Enable = 1, this field is automatically set by a value specified in the one of Preset Value registers.
3 2 1 0 |
| 3 | V1P8_SIGNAL_ENA | R/W | 0h |
This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V.
1.8V regulator output shall be stable within 5ms. Host Controller clears this bit if switching to 1.8V signaling fails.
Clearing this bit from 1 to 0 starts changing signal voltage from 1.8V to 3.3V.
3.3V regulator output shall be stable within 5ms. Host Driver can set this bit to 1 when Host Controller supports 1.8V signaling [One of support bits is set to 1: SDR50, SDR104 or DDR50 in the Capabilities register] and the card or device supports UHS-I.
'0' 3.3V Signalling, '1' 1.8V Signalling
1 1.8V Signalling 0 3.3V Signalling |
| 2:0 | UHS_MODE_SELECT | R/W | 0h |
This field is used to select one of UHS-I modes or UHS-II mode.In case of UHS-I mode, this field is effective when 1.8V Signal-ing Enable is set to 1. In case of UHS-II mode, 1.8V Signaling
Enable shall be set to 0. Setting of this field is used to select one of preset values in UHS-I or UHS-II mode.
If Preset Value Enable in the Host Control 2 register is set to 1,Host Controller sets SDCLK/RCLK Frequency Select, Clock Generator Select in the Clock Control register and Driver
Strength Select according to Preset Value registers. In this case, one of preset value registers is selected by this field. Host Driver needs to reset SD Clock Enable before changing this field to avoid generating clock glitch. After setting this field, Host Driver sets SD Clock Enable again.
When SDR50, SDR104 or DDR50 is selected for SDIO card, interrupt detection at the block gap shall not be used. Read Wait timing is changed for these modes. Refer to the SDIO Specification Version 3.00 for more detail.
7 6 5 4 3 2 1 0 |