SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to enable Error Interrupt Signal register
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 003Ah |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | VENDOR_SPECIFIC | HOST | RESP | TUNING | ADMA | AUTO_CMD | |
| NONE | R/W | R/W | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| CURR_LIMIT | DATA_ENDBIT | DATA_CRC | DATA_TIMEOUT | CMD_INDEX | CMD_ENDBIT | CMD_CRC | CMD_TIMEOUT |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | NONE | 0h | Reserved |
| 14:13 | VENDOR_SPECIFIC | R/W | 0h | N/A Reset Source: vbus_amod_g_rst_n |
| 12 | HOST | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 11 | RESP | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 10 | TUNING | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 9 | ADMA | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 8 | AUTO_CMD | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 7 | CURR_LIMIT | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 6 | DATA_ENDBIT | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 5 | DATA_CRC | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 4 | DATA_TIMEOUT | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 3 | CMD_INDEX | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 2 | CMD_ENDBIT | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 1 | CMD_CRC | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 0 | CMD_TIMEOUT | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |