SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to enable the Normal Interrupt Signal register
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0038h |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| BIT15_FIXED0 | BOOT_COMPLETE | RCV_BOOT_ACK | RETUNING_EVENT | INTC | INTB | INTA | CARD_INTERRUPT |
| R | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| CARD_REMOVAL | CARD_INSERTION | BUF_RD_READY | BUF_WR_READY | DMA_INTERRUPT | BLK_GAP_EVENT | XFER_COMPLETE | CMD_COMPLETE |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | BIT15_FIXED0 | R | 0h | The HD shall control error Interrupts using the Error Interrupt Signal Enable register. Reset Source: vbus_amod_g_rst_n |
| 14 | BOOT_COMPLETE | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 13 | RCV_BOOT_ACK | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 12 | RETUNING_EVENT | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 11 | INTC | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 10 | INTB | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 9 | INTA | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 8 | CARD_INTERRUPT | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 7 | CARD_REMOVAL | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 6 | CARD_INSERTION | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 5 | BUF_RD_READY | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 4 | BUF_WR_READY | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 3 | DMA_INTERRUPT | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 2 | BLK_GAP_EVENT | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 1 | XFER_COMPLETE | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 0 | CMD_COMPLETE | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |