SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to program DMA modes, LED Control, Data Transfer Width, High Speed Enable, Card detect test level and signal selection
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0028h |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| CD_SIG_SEL | CD_TEST_LEVEL | EXT_DATA_WIDTH | DMA_SELECT | HIGH_SPEED_ENA | DATA_WIDTH | LED_CONTROL | |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | CD_SIG_SEL | R/W | 0h | This bit selects source for card detection. '0' SDCD# is selected [for normal use] '1' The card detect test level is selected Reset Source: vbus_amod_g_rst_n |
| 6 | CD_TEST_LEVEL | R/W | 0h | This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. Generates [card ins or card removal] interrupt when the normal int sts enable bit is set. '0' No Card '1' Card Inserted Reset Source: vbus_amod_g_rst_n |
| 5 | EXT_DATA_WIDTH | R/W | 0h |
This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the Capabilities register. If a device supports 8-bit bus mode, this bit may be set to 1. If this bit is 0, bus width is controlled by Data Transfer Width in the Host Control 1 register.This bit is not effective when multiple devices are installed on a bus slot [Slot Type is set to 10b in the Capabilities register]. In this case, each device bus width is controlled by Bus Width Preset field in the Shared Bus register.
1 8-bit bus width
0 Bus width is selected by data transfer
width |
| 4:3 | DMA_SELECT | R/W | 0h | This field is used to select DMA type. The Host Driver shall check support of DMA modes by referring the Capabilities register. Selected DMA is enabled by DMA Enable of the Transfer Mode register in SD mode and DMA Enable of UHS-II Transfer Mode register in UHS-II mode. [1] Up to Version 3.00 When Host Version 4 Enable is set to 0, setting of this field is compatible to Host Controller Version 3.00.SDMA is initiated by writing to the Command register when this field is set to 00b and the SDMA System Address regis-ter [32-bit] is used. SDMA does not support 64-bit address-ing.ADMA2 is initiated by writing to the Command register when this field is set to 10b or 11b. Lower 32-bit of the ADMA Sys-tem Address register is used when this field is set to 10b and 64-bit of the ADMA System Address register is used when this field is set to 11b. Support of 64-bit System Addressing is indicated by 64-bit System Address Support for V3 in the Capabilities register. 64-bit AMDA2 uses 96-bit Descriptor. 00 - SDMA is selected 01 - 32-bit Address ADMA1 is selected 10 -32-bit Address ADMA2 is selected 11 - 64-bit Address ADMA2 is selected [Optional] [2] Version 4.00 or later When Host Version 4 Enable is set to 1, setting of this field is changed as follows. SDMA is initiated by Host Driver writes to the Command reg-ister when this field is set to 00b.ADMA2 is initiated by Host Driver writes to the Command register when this field is set to 10b or 11b and by ADMA3 sets to the ADMA System Address register when this field is set to 11b. ADMA3 is initiated by Host Driver writes to the ADMA3 IDAddress register when this field is set to 11b. 00 - SDMA is selected 01 - Not Used [New assignment is not allowed] 10 - ADMA2 is selected [AMDA3 is not supported or dis-abled] 11 - ADMA2 or ADMA3 is selected Support of 64-bit DMA and 128-bit Descriptor is indicated by 64-bit System Address Support for V4 in the Capabilities register. If the support bit is set to 1, all supported DMAs [depends on Support, ADMA2 Support and ADMA3 Sup-port] shall support 64-bit addressing. 64-bit Addressing in the Host Controller 2 register selects either 32-bit or 64-bit system addressing of DMAs. Reset Source: vbus_amod_g_rst_n |
| 2 | HIGH_SPEED_ENA | R/W | 0h |
This bit is optional. Before setting this bit, the HD shall check the High Speed Support in the capabilities register. If this bit is set to 0 [default], the HC outputs CMD line and DAT lines at the falling edge of the SD clock [up to 25 MHz/20MHz for MMC]. If this bit is set to 1, the HC outputs CMD line and DAT lines at the rising edge of the SD clock [up to 50 MHz for SD/52MHz for MMC]/ 208Mhz [for SD3.0]
If Preset Value Enable in the Host Control 2 register is set to 1, Host Driver needs to reset SD Clock Enable before changing this field to avoid generating clock glitches. After setting this field, the Host Driver sets SD Clock Enable again.
This bit is not effective in UHS-II mode.
1 0 |
| 1 | DATA_WIDTH | R/W | 0h |
This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card.
This bit is not effective in UHS-II mode.
1 0 |
| 0 | LED_CONTROL | R/W | 0h |
This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands, this bit can be set during all transactions. It is not necessary to change for each transaction.
1 0 |