SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to control the operations of data transfers
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 000Ch |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | RESP_INTR_DIS | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| RESP_ERR_CHK_ENA | RESP_TYPE | MULTI_BLK_SEL | DATA_XFER_DIR | AUTO_CMD_ENA | BLK_CNT_ENA | DMA_ENA | |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | RESP_INTR_DIS | R/W | 0h |
Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error,sets
this bit to 0 and waits Command Complete Interrupt and then checks the response register. If Host Controller checks response error, sets this bit to 1 and sets Response Error Check Enable to 1. Command Complete Interrupt is disabled by this bit regardless of Command Complete Signal Enable.
1 Disable Response Interrupt 0 Enable Response Interrupt |
| 7 | RESP_ERR_CHK_ENA | R/W | 0h |
Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked.If Host Driver checks response error, this bit is set to 0 and Response Interrupt Disable is set to 0.If Host Controller checks response error, sets this bit to 1 and sets Response Interrupt Disable to 1. Response Type R1 / R5 selects either R1 or R5 response type. If an error is detected, Response Error Interrupt is generated in the Response Error Interrupt Status register.
1 Enable Response Error Check 0 Disable Response Error Check |
| 6 | RESP_TYPE | R/W | 0h |
When response error check is enabled, this bit selects either R1 or R5 response types. Two types of response checks are supported:
R1 for memory and R5 for SDIO.
Error Statuses Checked in R1
.Bit31 OUT_OF_RANGE
.Bit30 ADDRESS_ERROR
.Bit29 BLOCK_LEN_ERROR
.Bit26 WP_VIOLATION
.Bit25 CARD_IS_LOCKED
.Bit23 COM_CRC_ERROR
.Bit21 CARD_ECC_FAILED
.Bit20 CC_ERROR
.Bit19 ERROR
Response Flags Checked in R5
.Bit07 COM_CRC_ERROR
.Bit03 ERROR
.Bit01 FUNCTION_NUMBER
.Bit00 OUT_OF_RANGE
1 SDIO 0 Memory |
| 5 | MULTI_BLK_SEL | R/W | 0h |
This bit enables multiple block data transfers.
1 Multiple Block transfer 0 Single Block transfer |
| 4 | DATA_XFER_DIR | R/W | 0h |
This bit defines the direction of data transfers.
1 Read from Card to Host 0 Write from Host to Card |
| 3:2 | AUTO_CMD_ENA | R/W | 0h |
There are three methods to stop Multiple-block read and write operation.
[1] Auto CMD12 Enable:
Multiple-block read and write commands for memory require CMD12 to stop the operation. When this field is set to 01b, the Host Controller issues CMD12 automatically when last block transfer is completed. Auto CMD12 error is indicated to the Auto CMD Error Status register. The Host Driver shall not set this bit if the command does not require CMD12.
When Host Version 4 Enable =0, CMD12 is issued when 16-bit Block Count is expired. When Host Version 4 Enable =1, CMD12 is issued when 16-bit Block Count or 32-bit Block Count is expired.
[2] Auto CMD23 Enable:
When this bit field is set to 10b, the Host Controller issues a CMD23 automatically before issuing a command specified in the Command register. The Host Controller Version 3.00 and later shall support this function. The following conditions are required to use the Auto CMD23.
The following conditions are required to use the Auto CMD23.
Auto CMD23 Supported [Host Controller Version is 3.00 or later].
A memory card that supports CMD23 [SCR[33]=1].
If DMA is used, it shall be ADMA.
Only when CMD18 or CMD25 is issued.
Auto CMD23 can be used with or without ADMA. By writing the Command register, the Host Controller issues a CMD23 first and then issues a command specified by the Command Index in Com-mand register. If response errors of CMD23 are detected, the second command is not issued. A CMD23 error is indicated in the Auto CMD Error Status register.32-bit block count value for CMD23 is set to 32-bit Block Count [SDMA System Address] register.
[3] Auto CMD Auto Select [Version 4.10]
As CMD23 is optional for SD memory card except UHS 104 card, if card supports CMD23, Auto CMD 23 should be used instead of Auto CMD12. Host Controller Version 4.10 defines this Auto CMD Auto Select mode. Selection of Auto CMD depends on setting of CMD23 Enable in the Host Control 2 register which indicates whether card supports CMD23. If CMD23 Enable =1, Auto CMD23 is used and if CMD23 Enable =0, Auto CMD12 is used. In case of Version 4.10 or later, use of Auto CMD Auto Select is recommended rather than use of Auto CMD12 Enable or Auto CMD23 Enable.
3 2 1 0 |
| 1 | BLK_CNT_ENA | R/W | 0h |
This bit is used to enable the Block count register, which is only relevant for multiple block transfers. When this bit is 0, the Block Count register is disabled, which is useful in executing an infinite transfer.
1 Enable Block count 0 Disable Block count |
| 0 | DMA_ENA | R/W | 0h | DMA can be enabled only if DMA Support bit in the Capabilities register is set. If this bit is set to 1, a DMA operation shall begin when the HD writes to the upper byte of Command register [00Fh].
1 DMA mode is Enabled 0 DMA mode is Disabled |