SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0002h |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| SDMA_ADDRESS | |||||||
| R/W | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| SDMA_ADDRESS | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:0 | SDMA_ADDRESS | R/W | 0h | This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10. Reset Source: vbus_amod_g_rst_n |