SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Table 8-9 describes the events servicing in receiving mode.
| Step | Register/Bit Field/Programming Model | Value |
|---|---|---|
| Read interrupt status bit | MAILBOX_IRQ_STATUS_CLR_j[0 + y*2] | 0x1 |
| IF: Number of messages is not equal to 0? | MAILBOX_MSG_STATUS_y[2:0] NUM_MESSAGES | ≠0x0 |
| Read message | MAILBOX_MESSAGE_y[31:0] VALUE | 0x-- |
| ELSE | ||
| Write 1 to acknowledge interrupt | MAILBOX_IRQ_STATUS_CLR_j[0 + y*2] | 0x1 |
| ENDIF |