SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Figure 6-16 captures the NSF4V and GLBCE integration in the VISS pipe line. Both NSF4V and GLBCE can be enabled or disabled based on use case. By default, they are disabled. General Visual use cases require NDF4V and GLBCE (along with FCP.EE) to be enabled.
Figure 6-17 captures the RawHistogram and Dynamic White Balance block integration in NSF4V. Both DWB and RawHistogram can be enabled/disabled independent of NSF4V enable. When Histogram is enabled, minimum frame width must be 128 (required to initialize the histogram memory at the frame start).