The following procedure shall be applied to initialize the UFS host controller:
- Assert reset signal. For more information about
the UFS reset signal, see UFS0 Clocks and Resets.
- De-assert reset signal and wait for at least 4
interface clock cycles (see Figure 12-220). For more information about the UFS interface clock, see UFS0 Clocks
and Resets.
- Write appropriate value into the FS_HCLKDIV
register.
- Write a 1h to the FS_SS_CTRL[0] RST_N_PCS bit to
take UFS slave device out of reset.
- Write a 1h to the UFS_HCE register in order to
enable the UFS host controller. This triggers an autonomous basic
initialization of the local UIC layer. The initialization sequence shall
consist of a DME_RESET and a DME_ENABLE command. Further
commands, such as DME_SET commands may be added, depending on the
implementation needs. During the basic initialization sequence, the UFS_HCE
register is read as 0h.
- Wait until the UFS_HCE register is read as 1h
before continuing. This indicates that the basic initialization sequence is
completed.
- Additional commands, such as DME_SET commands may be sent from the system host to the UFS host controller to provide configuration flexibility.
- Optionally set the UFS_IE[10] UCCE bit to 1h in
order to enable the interrupt (UFS_IS[10] UCCS).
- Send DME_LINKSTARTUP command to start the link startup procedure.
- Completion of the DME_LINKSTARTUP command
sets the UFS_IS[10] UCCS bit and may flag an interrupt to the system host if
the UFS_IE[10] UCCE bit is set. This interrupt will be flagged independently
from the GenericErrorCode.
- In case the GenericErrorCode of the completed
DME_LINKSTARTUP command is SUCCESS, the UFS_HCS[0] DP bit
is set in addition to the UFS_IS[10] UCCS bit.
- Check the value of the UFS_HCS[0] DP bit and make
sure that there is a device attached to the Link. If presence of a device is
detected, go to step 13; otherwise, resend the DME_LINKSTARTUP
command after the UFS_IS[7] ULLS bit has been set to 1h (go to step
8). The UFS_IS[7] ULLS bit equal 1h indicates that the UFS Device is
ready for a link startup.
- Enable additional interrupts by programming the
UFS_IE register.
- Initialize the Interrupt Aggregation Control
register (UFS_UTRIACR) with the desired values for the threshold
(UFS_UTRIACR[12-8] IACTH) and timeout (UFS_UTRIACR[7-0] IATOVAL).
- For example, write value 81010664h to initialize with the following parameters:
- The UFS_UTRIACR[31] IAEN bit is set.
- The UFS_UTRIACR[24] IAPWEN bit is set.
- The UFS_UTRIACR[16] CTR bit is set.
- The UFS_UTRIACR[12-8] IACTH bit field is set to
6h.
- The UFS_UTRIACR[7-0] IATOVAL bit field is set to
64h (4.0 ms).
- Note: The UFS_UTRIACR register
initialization may be executed at any time when the Run/Stop register
(FS_UTRLRSR) is not enabled or when no requests are outstanding.
- Complete the UFS host controller configuration via UIC command interface if required.
- Allocate and initialize UTP Task Management Request List.
- Program the UTP Task Management Request List Base
Address (UFS_UTMRLBA) with a 32-bit address pointing to the starting address
of the UTP Task Management Request List created at the step 15.
- Allocate and initialize UTP Transfer Request List.
- Program the UTP Transfer Request List Base
Address (UFS_UTRLBA) with a 32-bit address pointing to the starting address
of the UTP Transfer Request List created at the step 17.
- Enable the UTP Task Management Request List by
setting the UTP Task Management Request List Run Stop register
(UFS_UTMRLRSR) to 1h. This operation allows the UFS host controller to begin
accepting UTP Task Management Request via the UTP Task Management Request
Door Bell mechanism (UFS_UTMRLDBR).
- Enable the UTP Transfer Request List by setting
the UTP Transfer Request List Run Stop register (UFS_UTRLRSR) to 1h. This
operation allows the UFS host controller to begin accepting UTP Transfer
Request via the UTP Transfer Request Door Bell mechanism (UFS_UTRLDBR).
- At this point, the UFS host controller is up and running.