SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The CLEC implements minimal memory protection checks. It relies on protection mechanisms outside to control accesses from various masters. Chip-level firewalls control which masters may access the CLEC. MMUs provide finer-grain control for programmable processors that access the CLEC.
Specifically, the CLEC returns the following errors:
Any further access control must be implemented with firewalls and/or MMU configuration outside the CLEC.