SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
All 3 alerts from the 5 temperature monitors are available as inputs of the mask and alert merging logic block of each voltage domain, such that the temperature monitors that are relevant to each voltage domain can be selected as the contributors to the generation of the 3 combined interrupts in each voltage domain. This logic is presented in Figure 5-7. The THERM_MAXTEMP_OUTRANGE_ALERT is not shown in this figure. Notice that the same temperature sensor can contribute to more than one voltage domain and each voltage domain can have multiple sensors contributing to the interrupt generation in that VD, see WKUP_VTM_VD_EVT_SET_j and WKUP_VTM_VD_EVT_CLR_j registers.
The interrupts are only active when the sensor is in continuous mode. A one-shot sampling of the sensor will not trigger any interrupts.
Table 5-26 presents the connection of VTM TEMPSENSOR registers groups to voltage domains.
Register Group | Voltage Domain | |||
---|---|---|---|---|
WKUP_VTM_TMPSENS_*_0 | Near MCU_R5FSS in VDD_MCU | |||
WKUP_VTM_TMPSENS_*_1 | On VDD_MCU / VDD_CPU boundary near A72 (in VDD_MCU) | |||
WKUP_VTM_TMPSENS_*_2 | Near GPU in VDD_CORE | |||
WKUP_VTM_TMPSENS_*_3 | On VDD_CORE / VDD_CPU boundary near C7x / MMA (in VDD_CORE) | |||
WKUP_VTM_TMPSENS_*_4 | On VDD_CORE / VDD_CPU boundary near A72 (in VDD_CORE) | |||
WKUP_VTM_TMPSENS_*_5 | On VDD_CORE / VDD_CPU boundary near C7x / MMA (in VDD_CORE) | |||
WKUP_VTM_TMPSENS_*_6 | Near LPDDR4 in VDD_CORE (DDR) |