SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Table 10-153 shows the differences between the SoC level DRUs and the rest DRUs in the device. The rest of the features and functionality is same as described in Section 10.4.1 and Section 10.4.3.
Feature | SoC Level DRUs | DMPAC_UTC_DRU | VPAC_UTC0_RT_DRU, VPAC_UTC1_NRT_DRU |
---|---|---|---|
Cache warm support | Y | Y | N |
Atomic direct TR submission | Y | N | N |
Nonatomic TR submission register sets | 3 | 0 | 0 |
Data reformat functions | Transpose | None | None |
Minimum transpose size | 32 bits | N/A | N/A |
Embedded firewall | Y | Y | N |
Event generation | Encoded | Bit vector | Bit vector |