During a hardware DFS operation, the FSP mode registers are used to switch from one frequency set to the other. Before a hardware frequency change can be requested, the following must be programmed:
- DDRSS_CTL_193[17-16] FSP0_FRC
- DDRSS_CTL_193[25-24] FSP1_FRC
- DDRSS_CTL_192[24] FSP_WR_CURRENT
- DDRSS_CTL_192[16] FSP_OP_CURRENT
- DDRSS_CTL_190[24] MR_FSP_DATA_VALID_F2
- DDRSS_CTL_190[16] MR_FSP_DATA_VALID_F1
- DDRSS_CTL_190[8] MR_FSP_DATA_VALID_F0
FSP mode register writes are required as part of the DFS operation. To accomplish this, three mode register writes are issued to MR13, and additional mode register write to each of the FSP mode registers. These commands are issued at three times:
- After frequency change entry and before the
memory is placed into self refresh the first mode register write to MR13 is
issued. This writes the value from the DDRSS_CTL_180[7-0] MR13_DATA_0 and
DDRSS_CTL_187[23-16] MR13_DATA_1 fileds for all bits other than the FSP-WR
bit which will be defined as opposite of the FSP-OP bit. Then mode register
writes to all the other FSP mode registers are issued.
- After the memory is in self-refresh, the MR13 is written again. This write causes the FSP-OP bit to toggle, and to set the VRCG bit. At this point, the frequency change should take place.
- After the frequency change, one final mode
register write to MR13 is performed to clear the VRCG bit. The DFS operation
will update the FSP mode registers and the DDRSS_CTL_192[8] FSP_STATUS bit
once it is complete.