SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The A72 cluster and each A72 CPU reside in a separate power domain, as follows:
There is a dedicated Local Power Sleep Controller (LPSC) for the A72 cluster and for each A72 core, as well. The LPSC assignment is as follows:
For more details on these LPSCs, including power-up/down sequences, see Power.