SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Figure 8-2 shows a high-level view of the MSMC module that includes the main interfaces, memory, and subunits.
MSMC directly incorporates on-chip SRAM controllers to provide the compute cluster with low-latency memory. In addition, the individual memory banks can maintain coherence with the connected caching masters as well as the system slave ports.