The Display Controller (DISPC) supports:
- An embedded DMA Controller with the following features:
- Support for 1D-only DMA transfers
- Support for 48b addressable memory space
- Support for memory fragmentation through external PAT (Page Address Translation) table at SoC level
- Integrated shared buffer management for pipelines within the same DMA controller group
- Support for up to 8K-pixels wide frame buffer for 8/16/32/64 bits per pixel (total buffer space requirement not exceeding the total DMA buffer size of the DISPC)
- Programmable DMA request management
- Programmable buffer thresholds for request priority
- Bandwidth limiter on write requests (insertion on idle cycles between requests)
- Self-refresh using the DMA buffers
- Arbitration between normal/low priority pipelines
- Support for source image flip along X and Y-axis
- Support for secure access to firewall protected frame buffer in DDR memory
- Two input display processing Video Pipelines, each supporting:
- Input RGB source pixel formats:
- Bitmap-1, Bitmap-2, Bitmap-4, Bitmap-8
- ARGB16-4444, ABGR16-4444, RGBA16-4444, RGB16-565, BGR16-565, ARGB16-1555, ABGR16-1555
- RGB16-565/BGR16-565 with a separate A8 plane
- RGB24-888, BGR24-888
- ARGB32-8888, ABGR32-8888, BGRA32-8888, RGBA32-8888, ARGB32-2101010, ABGR32-2101010
- ARGB64-16161616, RGBA64-16161616
- Additionally, equivalent RGBx, xRGB, xBGR, and BGRx pixel formats defined, considering that A component of RGBA, ARGB, ABGR, BGRA pixel formats is ignored by HW (for example, ARGB —> xRGB); ("A" can be ignored by not selecting Alpha pixel)
- Pre-multiplied ARGB/RGBA formats
- Input YUV source pixel formats:
- Packed: YUV422-UYVY, YUV422-YUV2
- 2-plane: YUV420-NV12, YUV420-NV21, YUV422-NV12, YUV422-NV21
- 8-bit per component support for all YUV formats
- 10-bit IMG pack-format and 12-bit TI fully packed format support for 420/422 (internally processed as 10-bit component data)
- 16-bit unpacked source format (internally processed as 10-bit component data)
- Programmable poly-phase filter (scaler):
- Independent horizontal and vertical re-sampling: up-sampling (up to x16) and down-sampling (down to x0.25)
- Maximum input width of 2048 pixels using ARGB pixels and 5-tap, 4096 pixels using YUV pixels and 5-tap, and 4096 pixels using ARGB pixels and 3-tap. No limitation on the input height.
- Alpha blending factor is re-scaled like the R, G and B color components
- Implementation with 16 phases with symmetrical coefficients
- Programmable color space conversion from YUV422/YUV420 (chroma upsampled to YUV444 using the scaler) into ARGB48-12121212
- Programmable VC1 range mapping
- Programmable Brightness/Contrast/Hue/Saturation
- Programmable Gamma Correction LUT
- Luma Key generation
- 10-bit processing pipeline
- Two input display processing Video Lite Pipelines, each supporting:
- Input RGB source pixel formats:
- Bitmap-1, Bitmap-2, Bitmap-4, Bitmap-8
- ARGB16-4444, ABGR16-4444, RGBA16-4444, RGB16-565, BGR16-565, ARGB16-1555, ABGR16-1555
- RGB16-565/BGR16-565 with a separate A8 plane
- RGB24-888, BGR24-888
- ARGB32-8888, ABGR32-8888, BGRA32-8888, RGBA32-8888, ARGB32-2101010, ABGR32-2101010
- ARGB64-16161616, RGBA64-16161616
- Additionally, equivalent RGBx, xRGB, xBGR, and BGRx pixel formats defined, considering that A component of RGBA, ARGB, ABGR, BGRA pixel formats is ignored by HW (for example, ARGB —> xRGB); ("A" can be ignored by not selecting Alpha pixel)
- Pre-multiplied ARGB/RGBA formats
- Input YUV source pixel formats:
- Packed: YUV422-UYVY, YUV422-YUV2
- 2-plane: YUV420-NV12, YUV420-NV21, YUV422-NV12, YUV422-NV21
- 8-bit per component support for all YUV formats
- 10-bit IMG pack-format and 12-bit TI fully packed format support for 420/422 (internally processed as 10-bit component data)
- 16-bit unpacked source format (internally processed as 10-bit component data)
- YUV420 to YUV422 chroma upsampling using an average filter
- YUV422 to YUV444 chroma upsampling using a 4-tap filter based on Catmull-Rom algorithm
- Programmable color space conversion from YUV422/YUV420 into ARGB48-12121212
- Programmable VC1 range mapping
- Programmable Brightness/Contrast/Hue/Saturation
- Programmable Gamma Correction LUT
- Luma Key generation
- 10-bit processing pipeline
- One Write-back (WB) pipeline, supporting:
- Destination RGB pixel formats:
- ARGB16-4444, ABGR16-4444, RGBA16-4444, RGB16-565, BGR16-565, ARGB16-1555, ABGR16-1555
- RGB24-888 (no support for BGR24-888)
- RGB16-565/BGR16-565 with a separate A8 plane
- ARGB32-8888, ABGR32-8888, BGRA32-8888, RGBA32-8888, ARGB32-2101010, ABGR32-2101010
- ARGB64-16161616, RGBA64-16161616
- Destination YUV pixel formats:
- Packed: YUV422-UYVY, YUV422-YUV2
- 2-plane: YUV420-NV12, YUV420-NV21, YUV422-NV12, YUV422-NV21
- Only 8-bit output support for YUV formats
- Programmable poly-phase filter (scaler):
- Independent horizontal and vertical re-sampling: up-sampling (up to x16) and down-sampling (down to x0.25). When the output format of the WB pipeline includes a format change RGB/YUV422 —> YUV420, the maximum downscaling provided by the WB scaler is x0.5.
- Maximum input width of 2048 pixels using ARGB pixels and 5-tap, 4096 pixels using YUV pixels and 5-tap, and 4096 pixels using ARGB pixels and 3-tap. No limitation on the input height.
- Alpha blending factor is re-scaled like the R, G and B color components
- Implementation with 16 phases with symmetrical coefficients
- Operation modes:
- Output capture mode (to save one of the display outputs)
- Memory-to-memory (M2M) mode (to save a M2M composition/conversion operation result)
- Four Overlay Managers (OVR), each supporting:
- Input pixel format: ARGB48-12121212
- Output pixel format: ARGB48-12121212 ("A" component data is only used for the Write-back path)
- Overlay of the input pipelines (fully mapped to all input pipelines)
- Up to 4 input layers blending, plus background layer
- Transparency color key (source and destination)
- Alpha blending support: Embedded pixel alpha (ARGB and RGBA), global pixel, and combination of global pixel and pixel alpha
- Z-order programmable (full flexibility)
- Color bar test pattern insertion
- Any overlay output can be selected to drive the Write-back pipeline
- Four Video Port (VP) display outputs, each supporting:
- 36-bit per pixel on the RGB output interface (12-bits per component)
- Independent programmable timing generator, supporting up to 600 MHz pixel clock video formats (actual support limited by the maximum pixel clock provided to DSS at SoC level)
- Independent programmable 10-bit gamma correction
- Independent programmable multiple cycles output format on 8/9/12/16-bit interface (TDM)
- Selection between RGB and YUV422 output pixel format (YUV422 only available when BT.656/BT.1120 output is enabled)
- Configurable VP output mode: progressive mode only on RGB output, or progressive/interlaced mode on BT.656/BT.1120 output
- Internal data check diagnostic features:
- Supports up to 4 programmable (position/size) check regions on the DISPC video port display outputs
- Support for 1 check region on each input video pipeline output
- MISR (Multiple Input Signature Register) used on each check region to perform data correctness check and/or freeze frame detection
- Local power management features:
- Low power saving modes
- Capability to associate all buffers with a single pipeline for a display self-refresh
- System interconnect ports:
- Two 128-bit VBUSM master interfaces for data read/write
- One 32-bit VBUSP slave interfaces for configuration
MIPI Display
Serial Interface (DSI) transmitter host controller supports:
- Compliance with MIPI DSI
v1.3.1 protocol specification and previous specifications
- Compliance with MIPI
Stereoscopic Display Formats (MIPI SDF v1.0) specification
- Video and command operational
modes
- Both burst and non-burst
modes for video mode data transmission (with either sync pulses or sync
events)
- Up to 4 virtual channels via
command mode
- Supports data
interleaving support for one synchronous stream (video mode) from
the display controller, and up to three interleaved asynchronous
streams (command mode) from the interconnect concurrently
- Supports data
interleaving for up to four interleaved asynchronous streams
(virtual channels in command mode) from the interconnect
- Bi-directional communication
and escape mode (only on Lane-0)
- Pixel clock rate range 25-330
MHz (10-bit/component, 4MPix @60fps performance). Actual performance is
limited by the maximum pixel clock provided to the DSI controller at SoC
level.
- Programmable display
resolutions with maximum clock rate not exceeding the total available
bandwidth over 4MPix @60fps (10-bit/component RGB)
- 16/18/24/30/36-bit RGB input
data formats for video mode
- RGB16, RGB18 packed, and
RGB24 input data formats for command mode
- All generic data types
defined by MIPI
- Display Command Set (DCS):
transparent to the protocol engine, no decoding and interpretation of the
information from and to the peripheral
- ECC on the APB interface
- Data splitter for 2-,3-, or
4-data lane configuration
- Connection to a single MIPI
D-PHY complex I/O through an 8-bit Protocol Peripheral Interface (PPI)
- Bus contention recovery
- Video mode pattern generator:
color bar pattern image and D-PHY BET testing pattern
- APB slave interface with
32-bit data and address for configuration
MIPI DSI
(Physical Layer) D-PHY module supports:
- Compliance with MIPI D-PHY
1.2 physical layer interface specification and features
- 1, 2 or 4 data lanes, in
addition to clock signaling
- Maximum data rate up to 2.5
Gbps per data lane
- Protocol Peripheral Interface
(PPI)
- HS continuous and burst
mode
- LP (Low-Power), ULPM
(Ultra-Lower Power Mode), and Shutdown modes
- Forward direction and reverse
direction escape modes (only on Lane-0)
- Automatic termination control
in both high-speed and low-power modes
- DSI D-PHY IO pad signals work
at/with electrical specification specified by requested standards
- Single 32-bit VBUSP slave
interface
The Embedded Display Port (eDP) transmitter host controller supports:
- Compliance with VESA Display Port (DP) 1.3 (with 1.4 DSC/FEC support) specification
- Compliance with VESA embedded Display Port (eDP) 1.4 specification
- Static configuration of either DP or eDP mode
- Link rates up to HBR3 (maximum application bandwidth up to 25.92Gbps)
- Pixel clock rate range 25-600 MHz (10-bit/component, 8MPix@60fps performance).
- Transceiver AUX CH (1 MHz Manchester II coding mode) for access of DPCD and EDID
- 8, 10, and 12 bpc (bits per component), in RGB/YCbCr444 colorimetry formats (CEA-861 compliant) and YCbCr422 (via simple decimation)
- Data splitter for 1-, 2-, or 4-data lane configuration
- SST (Single Stream Transport)
- MST (Multiple Stream Transport):
- Up to 4 video and up to 1 audio sources
- Support for up to 25 Gbps throughput (equivalent to approximately 4K + 2xFHD streams) use case
- HDCP support on one video source
- DSC (Display Stream Compression) support on one 4K or 2x2.5K streams
- HDCP 1.4 and HDCP 2.2 with True Random Number Generator (TRNG with 8 FRO)
- DSC (Display Stream Compression) encoded stream data transport via an embedded DSC core:
- Supports VESA DSC 1.1 compliant video compression at 2x~3x compression ratios
- Supports all DSC 1.1 mandatory encoding mechanisms (MMAP, BP, MPP and ICH)
- Supports configurable maximum display resolution up to 8Mpix @60fps including (but not limited to) 4K@60 (4096x2160), and up to 8K wide-aspect-ratio resolution displays
- Supports two hard encoder slices (peak pixel ratio <= 340MP/s on each slice)
- Supports 8 and 10 bits per video component
- Supports RGB/YCbCR4:4:4 video input format (Native Encoding) only
- Supports Dual pixel streams or Split panel input streams
- Supports dual or single transport link
- Forward Error Correction (FEC) encoder with/without DSC enabled in DP mode
- Various eDP specific features:
- eDP DPCD registers
- Full and Fast Link Training
- (Regional) backlights and multi-touch command over AUX channel
- Alternate Scrambler Reset
- Audio transport features:
- I2S (LPCM/IEC60948/619376) audio input stream
- Audio transport of uncompressed multichannel (up to eight channels) via SDP (Secondary-data Packet)
- Metadata transport via MSA (Main Stream Attribute) packet or via SDP
- Display Port transmitter functionalities:
- Scrambler
- 8/10-bit Encoder (in the DPTX core)
- Inter Lane Skew Insertion
- Training Pattern Generation – TPS1,2,3,4 PRBS7 and 80-bit custom training pattern generation (bypassing the scrambler and encoder)
- PAPB Interface:
- The primary APB slave port controls the HD Display controller from the host processor
- During the boot, the primary APB slave port enables access to the I-MEM and D-MEM, and to the full address space for debugging purposes
- After the boot, the primary APB slave port enables direct register access to designated HW modules and enables communication with uCPU through a mailbox channel
- SAPB Interface
- For configuring the embedded HDCP, this bus is considered as a secured APB to carry secured commands over the mailbox channel
- Internal diagnostic features:
- ECC on the critical memories
- Parity check on the configuration interface
- Encoder self-check diagnostics support in the DSC core
- Corrected/Uncorrected error interrupt generation
- Injection of ECC and parity errors
The DP (Physical Layer) SERDES and Aux PHY modules support:
- DP1.3 HBR3 and eDP1.4a HBR3 throughput
- 1, 2, or 4 lanes at 1.62 Gbps, 2.7 Gbps, 5.4 Gbps, and 8.1 Gbps per lane
- Additional link rates (2.16, 2.43, 3.24, 4.32 Gbps) per lane in eDP mode
- Reduced differential voltage swing (0.2/0.25/0.30/0.35/0.40/0.45) in eDP mode
- Hot Plug Detect (HPD) for connection detection and interrupt from sink
- Integrated Low Jitter, Fixed Bandwidth PLL
- 1 Mbps AUX PHY for link training, DPCD register access, HDCP authentication and EDID access.