The A72 CPU supports invasive and non-invasive debug modes. The invasive debug mode is intended primarily for run-control debugging. Invasive debug mode provides support for:
- Monitor mode: In monitor mode, a debug event causes a debug exception to occur. A debug exception that relates to instruction execution generates a prefetch abort exception. A debug exception that relates to a data access generates a data abort exception. A software handler can then take control to examine or alter the processor state. Monitor debug mode is essential in real-time systems where the processor cannot be halted to collect debug information.
- Halt mode: In halt mode, a debug event causes the processor to enter debug state. In debug state, the processor stops executing instructions from the location indicated by the program counter, but is instead controlled through the external debug interface, in particular using the Instruction Transfer Register (DBGITR)
Non-invasive debug includes all debug features that permit data and program flow to be observed, but that do not permit modification of the main processor state. Non-invasive debug mode support includes processor instruction trace, sample-based profiling, and performance monitoring.