SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Table 4-80 shows an overview of the MPU configuration. In the R5 MPU, higher numbered regions have priority, therefore in Table 4-80, where two regions overlap, the region on the right defines the memory attributes.
Memory Address | Regions | |||
---|---|---|---|---|
0x0000_0000 | Region 0 non-executable full access | Region 10 | ||
0x0000_003F | ||||
... | ||||
0x4101_0000 | Region 3 TCM User access | Region 4 TCM Priv access | ||
0x4101_0FFF | ||||
0x4101_1000 | ||||
0x4101_7FFF | ||||
... | ||||
0x4180_0000 | Region 1 ROM User access | Region 2 ROM Priv access | ||
0x4180_7FFF | ||||
0x4180_8000 | ||||
0x4183_FFFF | ||||
... | ||||
0x41C0_0000 | Region 5 RAM All access non-cacheable | |||
0x41CB_FFFF | ||||
0x41CC_0000 | Region 6 cacheable | |||
0x41CD_FFFF | ||||
0x41CE_0000 | Region 7 cacheable | |||
0x41CE_FFFF | ||||
0x41CF_0000 | Region 8 non-cacheable non-executable | |||
0x41CF_DFFF | ||||
0x41CF_E000 | Region 9 cacheable | |||
0x41CF_FFFF | ||||
... | ||||
0xFFFF_FFFF |