The C71 debug architecture provides
three basic visibility and control mechanisms:
- Core debug controller
- Defines a means of
supporting fundamental debug requirements such as:
- System
visibility: access to application visible resources, and
certain private resources
- Debug events:
breakpoints, triggers, and other requests to halt
- Run control:
run, single-step, halt
- Cross-triggering: input and output triggers that can be
used to alter or convey execution state
- Provides support for
the core debug modes:
- Halt/Stop
mode
- Real-time
mode
- Monitor/Embedded mode
- Trace subsystem
- Collects and exports
trace data over an ATB bus interface without intrusiveness to the
behavior of application code running on the CPU (real-time
trace)
- Real-time trace
allows the observation of:
- Program flow
(with or without the associated stall cycles)
- Global
timestamp associated with occurrence of trace events that
can be correlated across multiple cores
- Memory
reference info: any combination of PC of the instruction
packet generating memory reference, the memory reference
address, the memory reference size (8, 16, 32, 64, 128, 256,
512) and type (R/W), the memory reference read or write data
value (up to 64-bits only)
- Auxiliary events
- Streaming buffer parameters
- Trace can be stored
on-chip or exported off-chip (supported by a dedicated debug
cell)
- Triggering (AET): Facilitates
the debugging of complex issues by enabling features such as:
- Context sensitive
breakpoints (thread aware)
- Data watchpoints
- Chained
breakpoints
- Profiling counters
with watermark support
- Visibility into
events generated from within the CPU, across the C71SS, and external
to the C71SS
- Trace stream
filtering