SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
In NAVSS0, a total of Packet Tx channels are provided within the DMA for concurrent data transfers between memory mapped space and the Tx Per Channel Buffers. Each of these channels can be configured to operate as a packet oriented channel (uses queues/rings/descriptors/buffer) or as a Third Party DMA source channel (uses Transfer Request packets to control read operations). Depending on which channel mode is selected, when a Tx channel comes into context the work for that channel will either be dispatched to a Tx Packet DMA Unit or a Third Party Read Unit respectively.
The Tx channels are allocated as shown in Table 10-101.
DMA Channel | Function | Tx Queue (Ring) |
---|---|---|
0 | Tx Channel | 0 (Starting queue number in RINGACC for Tx channel 0 ) |
... | ... | ... |
Tx Channel |