SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
This section describes the PCIe subsystem application fields from an environment point of view (external connections).
Table 12-180 describes the SERDES signal names at device level related to PCIe subsystem and specifies their functions.
Device Level Signal | I/O(1) | Description |
---|---|---|
PCIE1_RXN0 | I | PCIe Lane 0 Receive Differential Data (-) |
PCIE1_RXP0 | I | PCIe Lane 0 Receive Differential Data (+) |
PCIE1_TXN0 | O | PCIe Lane 0 Transmit Differential Data (-) |
PCIE1_TXP0 | O | PCIe Lane 0 Transmit Differential Data (+) |
PCIE1_RXN1 | I | PCIe Lane 1 Receive Differential Data (-) |
PCIE1_RXP1 | I | PCIe Lane 1 Receive Differential Data (+) |
PCIE1_TXN1 | O | PCIe Lane 1 Transmit Differential Data (-) |
PCIE1_TXP1 | O | PCIe Lane 1 Transmit Differential Data (+) |
PCIE1_RXN2 | I | PCIe Lane 2 Receive Differential Data (-) |
PCIE1_RXP2 | I | PCIe Lane 2 Receive Differential Data (+) |
PCIE1_TXN2 | O | PCIe Lane 2 Transmit Differential Data (-) |
PCIE1_TXP2 | O | PCIe Lane 2 Transmit Differential Data (+) |
PCIE1_RXN3 | I | PCIe Lane 3 Receive Differential Data (-) |
PCIE1_RXP3 | I | PCIe Lane 3 Receive Differential Data (+) |
PCIE1_TXN3 | O | PCIe Lane 3 Transmit Differential Data (-) |
PCIE1_TXP3 | O | PCIe Lane 3 Transmit Differential Data (+) |
PCIE1_CLKREQn | I/O | PCIe sideband signal for negotiation of L1
Substate entry/exit. The PCIE1_CLKREQn pin operates as an active low open-drain bidirection reference clock request pin. 1 = no request for clock; 0 = request for clock |