SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Clocks | |
Module Clock Input | Description |
CPPI_ICLK | CPPI packet streaming interface clock (320-MHz). Main clock for CPSW0. |
GMII_RFT_CLK | 125-MHz GMII Gigabit mode clock. |
RGMII_MHZ_5_CLK | 5-MHz RGMII reference clock. |
RGMII_MHZ_50_CLK | 50-MHz RGMII reference clock. |
RGMII_MHZ_250_CLK | 250-MHz RGMII reference clock. |
RMII_MHZ_50_CLK | 50-MHz RMII reference clock. |
CPTS_RFT_CLK | CPTS IEEE 1588 clock. |
GMII1_MT_CLK | |
GMII2_MT_CLK | |
GMII3_MT_CLK | |
GMII4_MT_CLK | |
GMII5_MT_CLK | |
GMII6_MT_CLK | |
GMII7_MT_CLK | |
GMII8_MT_CLK | |
GMII1_MR_CLK | |
GMII2_MR_CLK | |
GMII3_MR_CLK | |
GMII4_MR_CLK | |
GMII5_MR_CLK | |
GMII6_MR_CLK | |
GMII7_MR_CLK | |
GMII8_MR_CLK | |
RGMII_RXC_I | RGMII reference clock that provides the timing reference for receive operations. |
RGMII_TXC_O | RGMII transmit reference clock. |
MDIO_MCLK | Management data clock (MDIO_MCLK). The MDIO data clock is sourced by the MDIO module on the system. It is used to synchronize MDIO data access operations done on the MDIO pin. |
Resets | |
Module Reset Input | Description |
CPSW0_RST | Module Reset |
Interrupt Requests | ||
Module Interrupt Signal | Description | Type |
CPSW0_STAT_PEND_0 | CPSW0 statistic pending interrupt 0 | Level |
CPSW0_MDIO_PEND_0 | CPSW0 MDIO interrupt | Level |
CPSW0_EVNT_PEND_0 | CPSW0 event pending interrupt | Level |
CPSW0_ECC_SEC_PEND_0 | CPSW0 SEC ECC error interrupt | Level |
CPSW0_ECC_DED_PEND_0 | CPSW0 DED ECC error interrupt | Level |
Time Sync and Compare Events | ||
Module Event | Description | Type |
CPSW0_CPTS_COMP_0 | CPSW0 compare event interrupt | Edge |
CPSW0_CPTS_GENF0_0 | CPSW0 CPTS generator function event interrupt 0 | Edge |
CPSW0_CPTS_GENF1_0 | CPSW0 CPTS generator function event interrupt 1 | Edge |
CPSW0_CPTS_SYNC_0 | CPSW0 CPTS sync event interrupt | Edge |