SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The UFS subsystem includes one UFS 2.1 host controller with an integrated M-PHY. The UFS host controller is a standard-based serial interface engine.
The UFS host controller is compliant with the Universal Flash Storage (UFS) Specification and UFS Host Controller Interface (UFSHCI) Specification (see Table 12-298).
Figure 12-215 shows the UFS subsystem block diagram.
Figure 12-216 presents an example of UFS Integrated Protocol Stack (IPS) subsystem.
The UFS host controller is provided with additional hierarchy to support M-PHY integration.
These additional levels of hierarchy make up the IPS. Both the UFS host controller and the M-PHY share the same control interface (APB) and in further description is assumed they are mapped into single area in APB subsystem.
Figure 12-217 shows UFS controller block diagram.
Figure 12-218 presents an example of UFS system level block diagram.
Figure 12-219 shows UFS system model. The application layer of the UFS host controller connects to a UniPro protocol stack and M-PHY, both of which can be considered part of the UFS host controller.