SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Table 12-188 and Table 12-189 show the bus error mapping to/from the AXI interface on the PCIe controller to the system VBUSM interfaces.
The AXI2VBUSM bridge maps the bus errors on the ingress AXI interface to the VBUSM master interface as shown in the table below.
VBUSM | AXI | ||
---|---|---|---|
Code | Error | Code | Error |
0 (decimal) | Success | 0h | OKAY |
1 (decimal) | N/A | 3h | N/A |
2-3 (decimal) 7 (decimal) | All Others | 2h | SLVERR |
The VBUSM2AXI bridge maps the bus errors on the eggress VBUSM slave interface to the AXI interface as shown in the table below.
AXI | VBUSM | ||
---|---|---|---|
Code | Error | Code | Error |
N/A | N/A | 2 (decimal) | Protection Error |
0h | OKAY | 0 (decimal) | Success |
3h | DECERR | 1 (decimal) | Addressing Error |
2h | SLVERR | 1 (decimal) | Addressing Error |