SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The HBMC may assert the memory interrupt based on the status of the memory transaction. Software needs to handle this interrupt using the MCU_FSS0_HPB0_MC_ISR register. The MCU_FSS0_HPB0_MC_ISR register can provide the status information to determine the cause of the interrupt.