DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 0 | 202 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 1 | 3 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 2 | 16 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 3 | 22 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 4 | 202 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 5 | 3 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 6 | 16 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 7 | 22 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 8 | 202 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 9 | 3 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 10 | 16 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 11 | 22 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 12 | 202 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 13 | 3 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 14 | 16 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 15 | 22 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 16 | 202 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 17 | 3 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 18 | 16 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 19 | 22 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 20 | 238 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 21 | 22 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 22 | 4 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 23 | 16 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 24 | 22 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 25 | 238 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 26 | 22 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 27 | 4 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 28 | 16 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 29 | 22 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 30 | 238 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 31 | 22 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 32 | 4 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 33 | 16 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 34 | 22 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 35 | 238 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 36 | 22 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 37 | 4 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 38 | 16 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 39 | 22 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 40 | 238 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 41 | 22 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 42 | 4 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 43 | 16 | Parity |
DRU_R30_UTC_32CH_CORE_CMD_EDC_CTRL_0 | 44 | 22 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 0 | 8 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 1 | 16 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 2 | 12 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 3 | 4 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 4 | 5 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 5 | 3 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 6 | 2 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 7 | 1 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 8 | 1 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 9 | 1 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 10 | 1 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 11 | 16 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 12 | 16 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 13 | 1 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 14 | 16 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 15 | 8 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 16 | 5 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 17 | 1 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 18 | 16 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 19 | 8 | Parity |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 20 | 1 | Redundant |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 21 | 1 | Redundant |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 22 | 1 | Redundant |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 23 | 1 | Redundant |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 24 | 1 | Redundant |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 25 | 1 | Redundant |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 26 | 1 | Redundant |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 27 | 32 | EDC |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 28 | 32 | EDC |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 29 | 32 | EDC |
DRU_R30_UTC_32CH_CORE_PSIL_CMD_EDC_CTRL_0 | 30 | 32 | EDC |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 0 | 203 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 1 | 3 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 2 | 16 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 3 | 22 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 4 | 203 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 5 | 3 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 6 | 16 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 7 | 22 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 8 | 203 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 9 | 3 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 10 | 16 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 11 | 22 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 12 | 203 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 13 | 3 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 14 | 16 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 15 | 22 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 16 | 203 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 17 | 3 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 18 | 16 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 19 | 22 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 20 | 239 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 21 | 22 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 22 | 4 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 23 | 16 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 24 | 22 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 25 | 239 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 26 | 22 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 27 | 4 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 28 | 16 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 29 | 22 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 30 | 239 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 31 | 22 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 32 | 4 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 33 | 16 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 34 | 22 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 35 | 239 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 36 | 22 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 37 | 4 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 38 | 16 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 39 | 22 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 40 | 239 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 41 | 22 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 42 | 4 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 43 | 16 | Parity |
DRU_R30_UTC_64CH_CORE_CMD_EDC_CTRL_0 | 44 | 22 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 0 | 8 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 1 | 16 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 2 | 12 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 3 | 4 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 4 | 5 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 5 | 3 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 6 | 2 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 7 | 1 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 8 | 1 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 9 | 1 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 10 | 1 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 11 | 16 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 12 | 16 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 13 | 1 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 14 | 16 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 15 | 8 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 16 | 5 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 17 | 1 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 18 | 16 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 19 | 8 | Parity |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 20 | 1 | Redundant |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 21 | 1 | Redundant |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 22 | 1 | Redundant |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 23 | 1 | Redundant |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 24 | 1 | Redundant |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 25 | 1 | Redundant |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 26 | 1 | Redundant |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 27 | 32 | EDC |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 28 | 32 | EDC |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 29 | 32 | EDC |
DRU_R30_UTC_64CH_CORE_PSIL_CMD_EDC_CTRL_0 | 30 | 32 | EDC |