The STM_SS is a simple subsystem that is based on
the Arm System Trace Macrocell v500 (STM500). It provides the following major
features:
- A memory mapped interface for generating STP messages
- Instrumented SW can post high-level messages to the STM interface
- Messages are encoded as MIPI STP with unique IDs based on RouteID of the initiating master
- A debug time input interface for providing timestamp information to the STP stream
- Universal debug time is used to tag the message
- An ATB master for exporting the STP stream to the SoC trace infrastructure
- SOC_DEBUGCELL for on-chip capture or transfer to
functional domain for export (PCIE, Ethernet, etc)
- DEBUGSS for dedicated pin export
- CTI triggers for controlling trace flow
The Arm STM500 is a module that allows system
level masters to generate STP messages via memory-mapped access to a stimulus port. The
addresses used for these accesses control the following:
- Type and size of the STP data messages message generated
- Whether a debug timestamp is required
- Trace source (that is, STP master and channel)
- Behavior of the stimulus port (blocking/non-blocking)
Note: For more details on STM500 functionality, see ARM CoreSight STM-500 System Trace Macrocell Technical Reference Manual.
The STM_SS additionally provides the following functionality:
- Protocol bridging for the STM stimulus port (VBUSM-to-AXI on the STM)
- Address lookups to convert VBUSM RouteID values to extended AXI address bits for delineating STP masters on the STM AXI stimulus port
- Configuration port mapping and protocol conversion (VBUSP-to-APB for STM and CTI)
- Conversion of gray encoded global debug time to binary time
- Local trigger conversion to CS compatible trigger channels interface