SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The DISPC supports use-cases where portions of a single display (driven out of single OVR and VP) are controlled by multiple host processors (or virtual machines). In such a case, having a single GO bit per VP (display output) would result in partial updates of a particular pipeline register configuration on a frame boundary. The DISPC provides the additional capability to sync register configurations of each pipeline independently to a chosen frame boundary. This is achieved by setting the <PIPE> GO bit.
When the DSS0_COMMON_GLOBAL_GOBITMODE[0] MODE register bit is set, the individual pipeline register configurations are synced (shadow to work copy) only on frame boundaries where the DSS0_VID_PIPE_GO[0] GOBIT register bit of each used pipeline is set. The scheme is as shown in Figure 12-418.