SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
There are several DPHY_RX modules integrated in the device MAIN domain. Figure 12-504 shows the integration of DPHY_RX modules.
Table 12-471 through Table 12-472 summarize the integration of DPHY_RX in the device MAIN domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
DPHY_RX0 | PSC0 | PD2 | LPSC58 | CBASS0 |
DPHY_RX1 | PSC0 | PD2 | LPSC59 | CBASS0 |
Clocks | ||
Module Instance | Module Clock Input | Description |
DPHY_RX0 | DPHY_RX_MAIN_CLK | Main functional clock. |
CSI_RX_BYTE_CLK | The byte clock is the clock supplied by the DPHY_RX. | |
DPHY_RX1 | DPHY_RX_MAIN_CLK | Main functional clock. |
CSI_RX_BYTE_CLK | The byte clock is the clock supplied by the DPHY_RX. | |
Resets | ||
Module Instance | Module Reset Input | Description |
DPHY_RX0 | DPHY_RX_RST | Asynchronous module global reset. |
DPHY_RX1 | DPHY_RX_RST | Asynchronous module global reset. |
For more information on the interconnects, see System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Device Configuration.