SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
RAM ID Name | RAM ID | ECC Type | Inject Type | Accessible Flag | Max Number of Checkers |
---|---|---|---|---|---|
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 0 | EDC Interconnect | Inject with error capture | Yes | 24 |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 1 | EDC Interconnect | Inject with error capture | Yes | 87 |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 2 | EDC Interconnect | Inject with error capture | Yes | 31 |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 3 | EDC Interconnect | Inject with error capture | Yes | 36 |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_EDC_CTRL_0 | 4 | EDC Interconnect | Inject with error capture | Yes | 75 |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 5 | EDC Interconnect | Inject with error capture | Yes | 17 |
Protected Interconnect | Group ID | Width | Checker Type |
---|---|---|---|
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 0 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 1 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 2 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 3 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 4 | 6 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 5 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 6 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 7 | 2 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 8 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 9 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 10 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 11 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 12 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 13 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 14 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 15 | 6 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 16 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 17 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 18 | 2 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 19 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 20 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 21 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 22 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 | 23 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 0 | 24 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 1 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 2 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 3 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 4 | 15 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 5 | 10 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 6 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 7 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 8 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 9 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 10 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 11 | 9 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 12 | 10 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 13 | 10 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 14 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 15 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 16 | 15 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 17 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 18 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 19 | 10 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 20 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 21 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 22 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 23 | 10 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 24 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 25 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 26 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 27 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 28 | 10 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 29 | 9 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 30 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 31 | 10 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 32 | 10 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 33 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 34 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 35 | 9 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 36 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 37 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 38 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 39 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 40 | 10 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 41 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 42 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 43 | 10 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 44 | 10 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 45 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 46 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 47 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 48 | 10 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 49 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 50 | 12 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 51 | 2 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 52 | 2 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 53 | 8 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 54 | 8 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 55 | 8 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 56 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 57 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 58 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 59 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 60 | 2 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 61 | 2 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 62 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 63 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 64 | 2 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 65 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 66 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 67 | 4 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 68 | 4 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 69 | 4 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 70 | 4 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 71 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 72 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 73 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 74 | 8 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 75 | 12 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 76 | 12 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 77 | 2 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 78 | 2 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 79 | 8 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 80 | 8 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 81 | 8 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 82 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 83 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 84 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 85 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 | 86 | 12 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 0 | 32 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 1 | 32 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 2 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 3 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 4 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 5 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 6 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 7 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 8 | 15 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 9 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 10 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 11 | 2 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 12 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 13 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 14 | 10 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 15 | 2 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 16 | 2 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 17 | 2 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 18 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 19 | 1 | Redundant |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 20 | 2 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 21 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 22 | 10 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 23 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 24 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 25 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 26 | 1 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 27 | 2 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 28 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 29 | 3 | Parity |
VDC_DDR_EW_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 | 30 | 2 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 0 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 1 | 32 | EDC |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 2 | 1 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 3 | 9 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 4 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 5 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 6 | 12 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 7 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 8 | 12 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 9 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 10 | 32 | EDC |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 11 | 1 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 12 | 10 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 13 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 14 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 15 | 12 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 16 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 17 | 12 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 18 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 19 | 32 | EDC |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 20 | 1 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 21 | 10 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 22 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 23 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 24 | 12 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 25 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 26 | 12 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 27 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 28 | 32 | EDC |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 29 | 1 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 30 | 10 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 31 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 32 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 33 | 12 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 34 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 | 35 | 12 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 0 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 1 | 15 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 2 | 1 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 3 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 4 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 5 | 1 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 6 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 7 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 8 | 2 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 9 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 10 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 11 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 12 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 13 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 14 | 12 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 15 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 16 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 17 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 18 | 10 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 19 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 20 | 12 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 21 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 22 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 23 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 24 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 25 | 12 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 26 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 27 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 28 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 29 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 30 | 12 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 31 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 32 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 33 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 34 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 35 | 12 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 36 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 37 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 38 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 39 | 10 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 40 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 41 | 12 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 42 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 43 | 1 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 44 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 45 | 10 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 46 | 6 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 47 | 7 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 48 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 49 | 26 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 50 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 51 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 52 | 26 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 53 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 54 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 55 | 26 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 56 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 57 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 58 | 26 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 59 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 60 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 61 | 26 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 62 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 63 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 64 | 26 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 65 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 66 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 67 | 1 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 68 | 1 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 69 | 32 | EDC |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 70 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 71 | 1 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 72 | 10 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 73 | 10 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 | 74 | 1 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 0 | 1 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 1 | 32 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 2 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 3 | 1 | Redundant |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 4 | 15 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 5 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 6 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 7 | 1 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 8 | 1 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 9 | 2 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 10 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 11 | 1 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 12 | 10 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 13 | 5 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 14 | 3 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 15 | 4 | Parity |
DDR_EW_WRAP_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 | 16 | 2 | Parity |