The SoC debug capabilities are centered
around the Debug Subsystem (DEBUGSS). The DEBUGSS works in conjunction with the debug
capabilities integrated in the various processing units (such as CPUs and hardware
accelerators) to provide a comprehensive hardware platform for a rich debug and development
experience.
The SoC debug framework provides support for
the following features:
- Top-level debug support
- IEEE 1149.1 (JTAG + boundary scan)
and IEEE 1149.6 (boundary scan extensions)
- Centralized debug access gateway
(DEBUGSS) that provides support for debug access and trace in multiple CPU core
subsystems
- JTAG can access all debug and
system resources
- Other system masters can also
access all debug resources (self-hosted debug)
- Direct debug master to system memory
that bypasses any CPU datapath used for debug
- Global execution and system level
debug triggering (simultaneous run/halt)
- Arm CoreSight cross trigger
architecture
- Channel Interface (CI)
- Cross Trigger Interface
(CTI), Cross Trigger Matrix (CTM)
- Arm/TI trigger merge at the
DEBUGSS level
- Trace architecture that includes
various trace sources, sinks and supporting modules
- Discrete event trace
- Counter, Timer, and System
Event Trace (CTSET) module
- CBA4 compliant bus probing
- CPTracer2 (CPT2) aggregators
and probes
- Three levels of bus probing
(SoC, MCU domain, MSMC)
- Software message trace
- Universal debug time distribution
for correlating various trace sources
- Wide Timestamp Interface
(WTI)
- Trace distribution via Arm
Advanced Trace Bus (ATB) network
- Trace storing into dedicated
on-chip Trace Buffer Router (TBR) modules
- Trace streaming off-chip
- Export via CoreSight Trace
Port Interface Unit (TPIU)
- Export via high-speed
functional interfaces (Ethernet, PCIe)
- Requires software
assistance
- Advanced debug power, clock and reset
management
- Ownership aware peripheral debug
events (suspend mapping)
- Authenticating a debug connection on
device configured for high-security (HS) operations
- Compute Cluster debug support
- A72SS
- Invasive debug (halt mode,
monitor mode)
- Non-invasive debug (processor
trace, performance monitoring)
- CoreSight Embedded Trace
Macrocell (ETM)
- Cross triggering via CoreSight
CTI and CTM
- C71SS
- Core debug
- Advanced Event Triggering
(AET)
- Real-time trace
- Physical address watchpoints
- Event analysis
- MSMC
- Bus probing
- Discrete event trace
- Cross triggering via CoreSight
CTI and CTM
- R5FSS debug support
- Invasive debug (halt mode, monitor
mode)
- Non-invasive debug (processor trace,
performance monitoring)
- CoreSight ETM-R5
- Cross triggering via CoreSight CTI
and CTM
- DMPAC debug support
- HWA basic debug (system visibility,
run control)
- Cross triggering
- Discrete event trace
- VPAC debug support
- HWA basic debug (system visibility,
run control)
- Cross triggering
- Discrete event trace
Figure 13-1 shows a high-level overview of the SoC debug framework.