SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Table 4-67 shows the boot parameter table for xSPI. Must be preceded with the common boot parameters described in Boot Parameter Table Common Header.
Byte Offset | Size (bytes) | Name | Default Value | Description |
---|---|---|---|---|
256 | 1 | Port | 0 | Physical port number |
257 | 1 | Mode on | From Pins | If non-zero the mode byte will be sent |
258 | 1 | Instruct Width | From Pins | Number of pins used to send instructions (1, 8) |
259 | 1 | Address Width | From Pins | Number of pins used to send address (1,8) |
260 | 1 | Data Width | From Pins | Number of pins used to received data (1,8) |
261 | 1 | Address Size | 24 | 24 or 32 bits are the valid address sizes |
262 | 1 | Mode | 0 | QSPI clock polarity and phase mode |
263 | 1 | CSEL | From Pins | Chip select number (0-n) not the bitfield |
264 | 1 | Read Cmd | From Pins | Command used to read read data |
265 | 1 | Mode byte | 0 | Value used for the mode byte (when active) |
266 | 1 | Dummy Cycles | From pins | Number of dummy cycles sent after the read command |
267 | 1 | clkRecovery | From pins | Clock recovery |
268 | 1 | dqsEnable | 0 | Enable dqs |
269 | 1 | ddrEnable | From pins | OSPI DDR mode operation |
270 | 2 | Module Freq | 0 | The QSPI module frequency after PLL enable, in kHz. If 0 the ROM uses the value from the module clock tables. |
272 | 4 | Bus Frequency | From pins | The QSPI bus frequency, in kHz |
276 | 4 | Delay | 0x08080808 or 0x01010101 | The chip select read delays. Default value is based on the read command |
280 | 1 | SFDP | From Pins | Enables SFDP parser for 1S-1S-1S to 8D-8D-8D switching |
282 | 4 | Tap Delay | 0xffffffff | The read tap selection. If 0xffffffff the ROM will scan the taps to find the best delay. The result will then overwrite the value in this table. |
286 | 4 | Internal Clk | From pins | 0 = external (dqs) 1 = internal |
290 | 4 | indac | From pins | When 0 XIP mode is used |
294 | 4 | Read Index | 0 | Index to the active read address |
298 | 4 | Read Addr 0 | 0 | The initial flash read address |
302 | 4 | Read Addr 1 | 0x400000 | Backup read address |