SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The VPAC subsystem can run up to 5 independent pipelines using the VPAC HWAs and UTC. These pipelines are completely independent from each other and their input output data management is handled by the HTS module. The thread management is flexible and supports different top level settings of resolution, frame rate, DDR data buffer address, etc.
The VPAC HTS module is used to implement the thread management and control triggering of processing threads within the VPAC subsystem. It is used to manage message transfer and control between VPAC and external host (that is, SoC level processor). HTS can also be used to handle writing LDC block data into the SoC level MSMC (L3 SRAM) and create block to row data for the VPAC MSC and NF processing without going through the external DDR memory.
The mapping of VPAC HWAs to HTS scheduler is shown inTable 6-39. Note that each HWA and spare scheduler has a spare socket on its consumer and producer side (not mentioned in below table) for future expansion. For more details, see Section VPAC Hardware Thread Scheduler (HTS).
HTS scheduler | VPAC HWA |
---|---|
HWA0 | VISS0 |
HWA1 | Reserved |
HWA2 | LDC0 |
HWA3 | Reserved |
HWA4 | MSC0 |
HWA5 | MSC1 |
HWA6 | NF |
HWA7 | N/A |
HWA8 | N/A |
DMA0-4 | VISS0 [c0,c1,c2,x,x] |
DMA8-10 | Reserved |
DMA32 | MSC0 [c0] |
DMA40 | MSC1 [c0] |
DMA48 | NF [c0] |
DMA56-59 | N/A |
DMA64-67 | N/A |
DMA240-245 | VISS0 [p0,p1,p2,p3,p4,p5] |
DMA256-261 | Reserved |
DMA272-275 | LDC0 [p0,p1,p2,p3] |
DMA288-291 | Reserved |
DMA304-313 | MSC0 [p0] / MSC1 [p0], |
MSC0 [p1] / MSC1 [p1], | |
... | |
MSC0 [p9] / MSC1 [p9], | |
DMA336 | NF [p0] |
DMA352-355 | N/A |
DMA368-371 | N/A |