SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The R5FSS has two physical and three logical low latency peripheral ports:
The CPU requires the Virtual Peripheral Port to be mapped to a subset of (or complete) range of the Normal Peripheral Port. The Virtual Peripheral Port is disabled by default, and must be enabled by a System Control Coprocessor register write.
On this Device, the Virtual Peripheral Port is mapped to the same base address and size of the normal peripheral port. Although possible, the user should not enable the virtual peripheral port because the virtual port supports fewer (3 versus 15) outstanding writes, and enabling it will impact performance.