Figure 10-11 shows a diagram of the overall Receive operation for Host flow mode.
When packet reception begins on a given channel, the port will begin by fetching the first descriptor + buffer from the Ring Accelerator using the Free Descriptor/Buffer Queue 0 Index that was initialized in the Rx Flow Table for the flow which is being used by the channel. If the SOP Buffer Offset in the Rx Flow Table entry is nonzero, then the port will begin writing data after the offset number of bytes in the SOP buffer. The port will then continue filling that buffer and will fetch additional descriptors + buffers as needed using the Free Descriptor/Buffer Queue 1, 2, and 3 indexes for the 2nd, 3rd, and remaining buffers in the packet.
A detailed summary is as follows:
- Host allocates, populates, and places pointers to free descriptor/buffer structures onto Rx Free Descriptor/Buffer Queues
- UDMA-P fetches packet descriptor pointer from RA
- UDMA-P reads the packet descriptor to obtain the packet info, buffer pointer, and size
- UDMA-P fills the buffer with received data
- If packet is not complete, UDMA-P fetches next buffer descriptor pointer from RA
- UDMA-P fills the buffer with received data
If the RX_DESC_TYPE field in the Rx Flow Register A is set to 0 (Normal Rx Host Mode), Steps 5-7 continue until all packet data is received at which point the Rx engine proceeds to step 8. If the RX_DESC_TYPE is set to 1 (Single Buffer Packet Host Mode) the Rx engine will proceed to step 8 skipping step 7.
- UDMA-P writes previous buffer descriptor to memory. This includes the following fields:
- Buffer information
- Buffer Pointer with the byte aligned address of the chunk of buffer data
- Buffer Length with the number of bytes in the chunk of buffer data
- Pointer to next buffer descriptor in packet or 0 if this is the EOP buffer.
If the RX_DESC_TYPE field in the Rx Flow Register A is set to 0 (Normal Rx Host Mode), Steps 5-7 continue until all packet data is received at which point the Rx engine proceeds to step 8. If the RX_DESC_TYPE is set to 1 (Single Buffer Packet Host Mode) the Rx engine proceeds to step 8 as soon as the first buffer is full. Any remaining data in the packet from the line is then received into one or more additional packets each exactly one Host buffer long.
The UDMA-P performs the following operations when the entire packet has been received:
- UDMA-P writes the packet descriptor to memory. This includes the following fields:
- Descriptor Type (set to Host)
- Packet Length indicating the total number of bytes that are to be read from all of the buffers for this packet.
- Source Tag
- Destination Tag (application specific)
- Packet Type
- Any protocol specific flags for the given packet type
- SOP buffer information
- Buffer Pointer with the byte aligned address of the chunk of buffer data
- Buffer Length with the number of bytes in the chunk of buffer data
- Any protocol specific words that are required for the given packet type
- Networking Stack Information (application specific and optional)
- Pointer to next buffer descriptor in packet or 0 if this is the EOP buffer.
- UDMA-P writes the packet descriptor pointer to the appropriate Rx Queue. The absolute Queue that each packet to be forwarded to on completion of reception will either be the Queue which that was specified in the rx_dest_qnum field in the Rx Flow Table entry or will be a queue which was provided via the PSI-L destination queue number override field.
- Once the packet pointer is written to the Ring Accelerator it will send an up event to the Interrupt Aggregator
- The Interrupt Aggregator upon receiving the up event will set the appropriate bit in the Interrupt Status Register indicated by the interrupt mapping table which will cause an interrupt to be asserted to the Host
- The Host will pop the packet pointer from the Rx Queue
- If the pop causes the queue to become empty, the Ring Accelerator will send a down event to the Interrupt Aggregator thus causing the associated bit to be cleared and also potentially clearing the interrupt to the Host.
The Ring Accelerator is responsible for indicating the status of the Receive Queues to other ports/embedded processors using out-of-band level sensitive status lines. These status lines are set anytime a queue is non-empty.