SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Table 10-106 shows the RINGACC configuration parameters in this SoC.
Module Instance | Parameters | ||
Ring Count | Number of Monitors | Proxy Target Base | |
NAVSS0_RINGACC0 | 32 | 0x000038000000 | |
MCU_NAVSS0_UDMASS_RINGACC0 | 286 | 32 | 0x00002B000000 |
Table 10-107 shows the MSRAM configuration parameters set during SoC design. MSRAM0 is accessible only from the ring accelerator (DST port).
Module Instance | Parameters | ||
Depth | Width | Base Address | |
NAVSS0_MSRAM0 | 4096 | 128 | 0x000030000000 |
MCU_NAVSS0_UDMASS_MSRAM0 | 3594 | 64 | 0x000028000000 |
MCU_NAVSS0_UDMASS_MSRAM1 | 4096 | 64 | 0x000028010000 |