SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The MSMC has scrubbing engine that periodically cycles through each location of each memory bank in the MSMC, reading and correcting the data, recalculating the parity bits for the data and storing the data and parity information.
The frequency with which each scrubbing cycle is initiated and the delay between each burst by the scrubbing engine is programmed using the MSMC_SMEDCC register. The MSMC_SMEDCC[7-0] REFDEL bitfield controls the number of MSMC_CLK cycles between each scrub. To prevent the bursts from the scrubbing engine from posing a significant performance impact, the value in the REFDEL field is pre-scaled by 1024 in functional mode. A value of 0 is interpreted to be the same as a value of 1. At reset, REFDEL = 0 and a new scrub burst is issued 1024 cycles after the previous one ends. The operation of the scrubbing engine is enabled by default at reset but may be disabled by setting the MSMC_SMEDCC[31] SEN bit to 0x0.